公开(公告)号：US20250077739A1

公开(公告)日：2025-03-06

申请号：US18727141

申请日：2022-11-10

Applicant: JFE STEEL CORPORATION

Inventor： Takeshi OGAWA ,  Satoshi SUMIKAWA ,  Yuji YAMASAKI ,  Toyohisa SHINMIYA

IPC: G06F30/23 ,  G06F30/17 ,  G06F113/24 ,  G06F119/02

Abstract: An analysis accuracy evaluation method includes: generating, based on measurement data obtained by measurement of a shape after die release of an actual press-formed part press-formed with a predetermined tool of press forming by utilization of an actual blank taken from a metal sheet having shape variation; generating an actual blank model having a same shape as the actual blank based on measurement data; acquiring a press-formed part shape after die release as an analysis press-formed part shape by performing, by using the actual blank model, a press-forming analysis of when press forming is performed with a model of a tool of press forming which model has a same shape as the predetermined tool of press forming; and comparing the actual press-formed part shape and the analysis press-formed part shape, obtaining a deviation amount of shape change of the both shapes, and evaluating accuracy of the press-forming analysis.

公开(公告)号：US12236177B2

公开(公告)日：2025-02-25

申请号：US17586516

申请日：2022-01-27

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Lawrence James Gewax ,  Timothy Paul Duryea

IPC: G06F30/33 ,  G06F30/327 ,  G06F30/367 ,  G06F30/398 ,  G06F119/02

Abstract: One example includes a method for validating a circuit design. The method includes providing a set of coded rules. Each of the coded rules can define conditions for circuit cells to qualify the circuit design as being radiation-hardened. The method also includes accessing a circuit design netlist associated with the circuit design from a circuit design database. The method also includes evaluating each of the circuit cells in the circuit design netlist with respect to each of the coded rules. The method further includes providing a circuit evaluation report comprising an indication of failure of a set of the circuit cells with respect to one or more of the coded rules in response to the evaluation.

公开(公告)号：US12182490B2

公开(公告)日：2024-12-31

申请号：US18316405

申请日：2023-05-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Song-Yi Han ,  Jae Min Kim ,  Jae Ho Kim ,  Ji-Seong Doh ,  Kang-Hyun Baek ,  Young Kyou Shin ,  Seong Hun Jang ,  Young Jun Cho ,  Yun Ji Choi

IPC: G06F30/398 ,  G06F30/12 ,  G06F119/02

Abstract: A semiconductor design automation system comprises a simulator configured to generate simulation data, a recovery module configured to correct a sampling error of the simulation data to generate recovery simulation data, a hardware data module configured to generate real data, a preprocessing module configured to preprocess the real data to generate preprocessed real data, a database configured to store the recovery simulation data and the preprocessed real data, a first graphic user interface including an automatic simulation generator configured to generate a machine learning model of the recovery simulation data and the preprocessed real data and generate predicted real data therefrom, and a second graphic user interface including a visualization unit configured to generate a visualized virtualization process result from the machine learning model.

公开(公告)号：US12175169B2

公开(公告)日：2024-12-24

申请号：US17073309

申请日：2020-10-17

Applicant: TECHNOLOGIES DUAL-ADE INC.

Inventor： Jeffrey Heckman ,  Anaele Pin

IPC: G06F30/20 ,  G06F30/10 ,  G06F30/23 ,  G06F111/10 ,  G06F119/02 ,  G06F113/08 ,  G06F119/08

Abstract: A method of evaluating a stress applied to components of a switchgear cabinet for sustaining an arc-flash with an arc-flash event simulation and energy transmission thereof is presented with steps comprising providing a location of the arc-flash in an internal volume of the switchgear cabinet, simulating the arc-flash as a local ambient boundary condition at the location of the arc flash with an input energy, diffusing the input energy in an air domain inside the switchgear cabinet, applying the input energy as a thermal history to specific arc-flash elements, multiplying the thermal history by specific heat to calculate energy units at the arc-flash, identifying a desired thermal energy magnitude and history of deposition and calibrating the desired thermal history to substantially match an estimated mechanical power generated by the arc-flash.

公开(公告)号：US12158800B2

公开(公告)日：2024-12-03

申请号：US18094986

申请日：2023-01-10

Applicant: Silicon Motion, Inc.

Inventor： Tsu-Han Lu ,  Hsiao-Chang Yen

IPC: G06F11/07 ,  G06F3/06 ,  G06F12/0837 ,  G06F12/0882 ,  G06F12/128 ,  G06F119/02

Abstract: A flash memory controller to be used in a storage device and coupled to a flash memory device of the storage device through a specific communication interface. The flash memory controller sends a debug injection command signal to the flash memory device through the specific communication interface to configure an operation of a debug circuit of the flash memory device to make the debug circuit automatically generate debug information of an access operation of the debug injection command signal sent from the flash memory controller, transmit the generated debug information from the flash memory device to the flash memory controller via the I/O control circuit and the specific communication interface, without controlling a memory cell array of flash memory device generating errors.

公开(公告)号：US20240371925A1

公开(公告)日：2024-11-07

申请号：US18771815

申请日：2024-07-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chia-Wei HSU ,  Bo-Ting CHEN ,  Jam-Wem LEE

IPC: H01L29/06 ,  G06F30/392 ,  G06F30/3953 ,  G06F30/398 ,  G06F119/02 ,  H01L23/522 ,  H01L23/528 ,  H01L27/02

Abstract: A semiconductor device includes a semiconductor substrate having a first protected circuit; a first guard ring; and a second guard ring adjacent to the first guard ring and around the first protected circuit. The second guard ring includes a first via tower configured to provide a first reference voltage; a second via tower configured to provide a second reference voltage different than the first reference voltage; and at least a third via tower configured to provide the first reference voltage.

公开(公告)号：US12086529B1

公开(公告)日：2024-09-10

申请号：US17691974

申请日：2022-03-10

Applicant: Cadence Design Systems, Inc.

Inventor： Igor Keller ,  Eric K. Anderson ,  Yang Gao

IPC: G06F30/398 ,  G06F30/3315 ,  G06F119/02

CPC classification number: G06F30/398 ,  G06F30/3315 ,  G06F2119/02

Abstract: Various embodiments provide for using a timing-based yield calculation to modify a circuit design, which can be part of an electronic design automation (EDA) system. For instance, some embodiments use a timing-based yield calculation to modify one or more portions of the circuit design to improve timing of the circuit design (e.g., slack, slew, delay, etc.), the timing-based yield calculation of the circuit design, or both.

公开(公告)号：US20240289509A1

公开(公告)日：2024-08-29

申请号：US18658500

申请日：2024-05-08

Applicant: DASSAULT SYSTEMES DEUTSCHLAND GMBH

Inventor： Hannes THIELHELM ,  Michael HANEL

IPC: G06F30/15 ,  G06F17/13 ,  G06F30/20 ,  G06F111/08 ,  G06F119/02

CPC classification number: G06F30/15 ,  G06F17/13 ,  G06F30/20 ,  G06F2111/08 ,  G06F2119/02

Abstract: A computer-implemented method for vehicle impact analysis including obtaining a B-Rep representing an outer surface of a vehicle, the B-Rep having faces and obtaining a radius value for a contact sphere. The method also includes determining one or more two-point-contact curves of the B-Rep for the radius value. The determining includes, for each respective two-point-contact curve, solving a respective differential equation based on the B-Rep. The method forms an improved solution for vehicle impact analysis.

公开(公告)号：US12066809B2

公开(公告)日：2024-08-20

申请号：US17470015

申请日：2021-09-09

Applicant: Chongqing University

Inventor： Shilong Wang ,  Chi Ma ,  Sibao Wang ,  Dechao Heng ,  Lingwan Zeng ,  Yong Yang ,  Canhui Yang

IPC: G05B19/40 ,  F16H57/01 ,  G05B19/404 ,  G05B19/406 ,  G06F30/10 ,  G06F30/27 ,  G06N5/01 ,  G06F119/02

CPC classification number: G05B19/404 ,  F16H57/01 ,  G05B19/406 ,  G06F30/10 ,  G06F30/27 ,  G06N5/01 ,  F16H2057/012 ,  G06F2119/02

Abstract: A method for identifying a critical error of a worm gear machine, step 1: obtaining an actual forward kinematic model T27a and an ideal forward kinematic model T27i from a coordinate system of a worm gear hob to a coordinate system of a worm gear, thereby establishing a geometric error-pose error model of the worm gear machine; step 2: regarding the geometric error-pose error model of the worm gear machine as a multi-input multi-output (MIMO) nonlinear system, and solving, by taking the geometric error of each motion axis of the worm gear machine as an input feature X, and a pose error between the worm gear hob and the worm gear as an output variable Y, an importance coefficient of each input feature with a random forest algorithm; and step 3: determining a critical error affecting a machining accuracy of the worm gear machine.

公开(公告)号：US20240265185A1

公开(公告)日：2024-08-08

申请号：US18638319

申请日：2024-04-17

Applicant: Tencent Technology (Shenzhen) Company Limited

Inventor： Shengming MA ,  Jianming WANG ,  Sainan HUAI ,  Shengyu ZHANG ,  Shuoming AN ,  Xiong XU ,  Dengfeng LI

IPC: G06F30/392 ,  G06F119/02

CPC classification number: G06F30/392 ,  G06F2119/02

Abstract: In a circuit layout processing method, an initial circuit layout of a chip is obtained. The initial circuit layout includes initial position information of a line in the chip. A correction value of the line is obtained. The correction value is set based on an etching processing error of the chip. A boundary of the line in the initial circuit layout is corrected based on the initial position information and the correction value to obtain a corrected circuit layout.