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21.发明申请公开(公告)号：US20220406252A1
公开(公告)日：2022-12-22
申请号：US17620195
申请日：2020-12-23
Inventor： Xuehuan FENG , Yongqian LI , Pan XU , Zhongyuan WU
IPC: G09G3/3233 , G09G3/3266
Abstract: A pixel circuit array, a display panel, a method for driving a pixel circuit array, and a method for driving a display panel are provided. The pixel circuit array may include: a first signal sensing line (SENSE1) and a second signal sensing line (SENSE2); and N pixel circuits arranged in a column. All of the N pixel circuits are divided into a first group and a second group, each pixel circuit in the first group is coupled to the first signal sensing line (SENSE1), and each pixel circuit in the second group is coupled to the second signal sensing line (SENSE2) different from the first signal sensing line (SENSE1), where N is a positive integer greater than 1.
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公开(公告)号：US20220384558A1
公开(公告)日：2022-12-01
申请号：US17771659
申请日：2021-06-15
Applicant: BOE Technology Group Co., Ltd.
Inventor： Pan XU , Dacheng ZHANG , Yicheng LIN , Yongqian LI
IPC: H01L27/32
Abstract: The present disclosure provides a display substrate and a display apparatus. The display substrate has a display region, and the display substrate includes a base substrate and a plurality of gate lines and a plurality of data lines on the base substrate; the plurality of gate lines and the plurality of data lines are arranged to cross each other to define a plurality of pixel regions, and a pixel unit is arranged in a pixel region of the plurality of pixel regions; each pixel unit includes a thin-film transistor and a light-emitting device in the display region; the display substrate further comprises a plurality of fan-out traces in the display region, wherein each fan-out trace of the plurality of fan-out traces is electrically connected to a data line corresponding to the fan-out trace, and is arranged in a different layer from the date lines and the gate lines.
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23.发明申请公开(公告)号：US20220309978A1
公开(公告)日：2022-09-29
申请号：US17556652
申请日：2021-12-20
Inventor： Xuehuan FENG , Yongqian LI
Abstract: The present disclosure provides display apparatuses, gate drive circuits, shift register units and driving methods thereof. The shift register unit includes: an outputting module, configured to output a composite output signal under a control of a potential of a pull-up node; a pull-up module, configured to charge the pull-up node under a control of a display control signal terminal and charge the pull-up node under a control of a potential of a black insertion node; a first reset circuit configured to, under a control of the reset signal terminal and the potential of the black insertion node, control a voltage control node to communicate with the pull-up node; a current-limiting circuit, connected between the voltage control node and a first voltage terminal; and a charging module, configured to charge the voltage control node under the control of the potential of the pull-up node.
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公开(公告)号：US20220285476A1
公开(公告)日：2022-09-08
申请号：US17630171
申请日：2021-04-12
Inventor： Yongqian LI , Zhenhua QIU , Ying WANG , Meng LI , Dongxu HAN , Dacheng ZHANG , Shi SUN
Abstract: Provided in the present disclosure are a display substrate and a preparation method therefor, and a display apparatus. The display substrate comprises a plurality of display units, each display unit comprising a display area and a transparent area, and the display area comprising a plurality of sub-pixels; each sub-pixel comprises a second metal layer and a third metal layer, the second metal layer comprising a first scanning line and a second scanning line defining a display row, the third metal layer comprising a first power source line, a second power source line, a compensation line, and a data line defining the plurality of sub-pixels; the first power source line, the second power source line, the compensation line, and the data line all comprise a vertical linear section and a horizontal polyline section.
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公开(公告)号：US20220123056A1
公开(公告)日：2022-04-21
申请号：US17280725
申请日：2020-05-15
Inventor： Meng LI , Yongqian LI , Jingquan WANG , Chen XU , Dacheng ZHANG , Zhidong YUAN , Can YUAN , Xuehuan FENG
Abstract: A display region includes a plurality of pixel driving circuitry setting regions arranged sequentially in a first direction, and each pixel driving circuitry setting region extends in a second direction intersecting the first direction. Each display circuitry includes a plurality of subpixels in one-to-one correspondence with the pixel driving circuitry setting regions, each subpixel includes a subpixel driving circuitry and a light-emitting element coupled to each other, the subpixel driving circuitry is located in a corresponding pixel driving circuitry setting region, the light-emitting element is located at a side of the subpixel driving circuitry away from the substrate, a width of the light-emitting element is greater than a width of the corresponding pixel driving circuitry setting region in the first direction, and a length of the light-emitting element is smaller than a length of the corresponding pixel driving circuitry setting region in the second direction.
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Patent Agency Ranking
公开(公告)号：US20220101796A1
公开(公告)日：2022-03-31
申请号：US17427607
申请日：2021-01-22
Inventor： Xuehuan FENG , Yongqian LI
IPC: G09G3/3266 , G11C19/28
Abstract: A shift register, a gate driving circuit and a gate driving method are provided. The shift register includes: a display pre-charging reset circuit, a display noise reduction circuit and an output circuit, the output circuit is provided with at least one signal output terminal, and includes at least one output sub-circuit; the display pre-charging reset circuit is configured to write a first scanning voltage into a pull-up node in response to a control of a first signal input terminal; and write a second scanning voltage into the pull-up node in response to a control of a second signal input terminal; the display noise reduction circuit is configured to write the second scanning voltage into a pull-down node in response to the control of the first signal input terminal; and write the first scanning voltage into the pull-down node in response to the control of the second signal input terminal.
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公开(公告)号：US20220084457A1
公开(公告)日：2022-03-17
申请号：US17424483
申请日：2020-08-24
Inventor： Xuehuan FENG , Yongqian LI
IPC: G09G3/20
Abstract: The disclosure provides a shift register, a drive method thereof, a gate drive circuit, and a display panel. The shift register comprises a first shift register unit and a second shift register unit. The first shift register unit comprises a first input circuit, a first output circuit, a first pull-down circuit and a unidirectional isolation circuit, the first input circuit is connected to a first input terminal and a first pull-up node, the first output circuit is connected to the first pull-up node, a first output terminal and a first clock terminal, and the first output terminal is connected to the first pull-down circuit by means of the unidirectional isolation circuit; and the second shift register unit comprises a second input circuit and a second output circuit, the second input circuit is connected to a second input terminal and a second pull-up node, the second output circuit is connected to the second pull-up node, a second output terminal and a second clock signal, and the second output terminal is connected to a node between the first pull-down circuit and the unidirectional isolation circuit.
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公开(公告)号：US20220013060A1
公开(公告)日：2022-01-13
申请号：US17294690
申请日：2020-08-20
Inventor： Xuehuan FENG , Yongqian LI
IPC: G09G3/20
Abstract: A shift register and a drive method therefor, and a gate drive circuit. The shift register includes: an input sub-circuit, a detection control sub-circuit, an output sub-circuit, a first reset sub-circuit, and a pull-down sub-circuit. The detection control sub-circuit is respectively connected to a random detection signal end (OE), a signal input end (INPUT), a first clock signal end (CLKA), a first reset end (RST1), and a pull-up node (PU), and is configured to provide a signal of the first clock signal end (CLKA) for the pull-up node (PU) under the control of the signal input end (INPUT), the random detection signal end (OE), the first clock signal end (CLKA), and the first reset end (RST1).
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公开(公告)号：US20220005413A1
公开(公告)日：2022-01-06
申请号：US17294676
申请日：2020-08-07
Inventor： Zhidong YUAN , Xuehuan FENG , Yongqian LI , Can YUAN , Meng LI , Dongxu HAN
IPC: G09G3/3241 , G09G3/3266
Abstract: A pixel circuit and a driving method thereof, and a display device, the pixel circuit being configured to drive a light-emitting element and including: a node control sub-circuit, which is configured to provide a first node with a signal of a data signal end and provide a second node with a signal of a control signal end under the control of a first scanning end; a driving sub-circuit, which is configured to provide the second node with a driving current under the control of the first node and the second node; a storage sub-circuit, which is configured to store electric charge between the first node and the second node; a reading sub-circuit, and the light-emitting element, which is electrically connected to the second node and a second power supply end, respectively.
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公开(公告)号：US20220005400A1
公开(公告)日：2022-01-06
申请号：US17279478
申请日：2020-05-25
Inventor： Xuehuan FENG , Yongqian LI
IPC: G09G3/20
Abstract: The present disclosure discloses a shift register, a gate driving circuit and a display device. The shift register includes a display pre-charge reset circuit, a sensing cascade circuit, a sensing pre-charge reset circuit, a pull-down control circuit and an output circuit, where the display pre-charge reset circuit, the sensing cascade circuit and the sensing pre-charge reset circuit share the same pull-down control circuit and the same output circuit, the output circuit is coupled to at least one signal output terminal, the output circuit includes output sub-circuits in one-to-one correspondence with the at least one signal output terminal, and each output sub-circuit is configured to write a driving clock signal into the corresponding signal output terminal in a display output stage and a sensing output stage in response to a control of a voltage of a pull-up node in an effective level state.
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