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公开(公告)号：US20240306457A1
公开(公告)日：2024-09-12
申请号：US18245134
申请日：2022-03-25
Inventor： Liu WU , Zhidong YUAN , Yongqian LI , Can YUAN , Chuanchuan CHANG , Jun LIU , Tao SUN
IPC: H10K59/131 , H10K59/12 , H10K59/88
CPC classification number: H10K59/1315 , H10K59/1201 , H10K59/88
Abstract: A display substrate and a manufacturing method therefor, and a display device. The display substrate includes: a base substrate including a special-shaped display area and a frame area located on one side of the special-shaped display area; and the special-shaped display area includes a first display area and a second display area on located on one side of the first display area, and the second display area is arranged in contact with the frame area; a group of data lines located on the base substrate and located in the first display area and the second display area; a group of fan-out lines located on a side of a layer where the group of data lines are located away from the base substrate, located in the first display area, and electrically connected to the data lines; and a group of dummy leads.
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公开(公告)号：US20240172480A1
公开(公告)日：2024-05-23
申请号：US17779143
申请日：2021-07-12
Inventor： Can YUAN , Yongqian LI , Maoning ZHANG , Chao JIAO , Zhidong YUAN , Dacheng ZHANG
IPC: H10K59/121 , H10K59/12 , H10K59/122 , H10K59/126 , H10K59/131 , H10K59/35 , H10K59/80
CPC classification number: H10K59/1216 , H10K59/1201 , H10K59/122 , H10K59/126 , H10K59/131 , H10K59/351 , H10K59/80524
Abstract: Provided is a display substrate and a manufacturing method therefor, and a display apparatus. The display substrate includes multiple sub-pixels, at least one sub-pixel includes a drive circuit layer disposed on the substrate, the drive circuit layer includes a ring storage capacitor constituting a pixel drive circuit; the ring storage capacitor includes a first electrode plate and a second electrode plate, wherein, the first electrode plate includes a first housing surrounding at least one first opening and the second electrode plate includes a second housing surrounding at least one second opening; an orthographic projection of the first housing on the substrate at least partially overlaps an orthographic projection of the second housing on the substrate, and the first housing and the second housing form a capacitor housing around at least one capacitor opening.
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公开(公告)号：US20240161691A1
公开(公告)日：2024-05-16
申请号：US17779576
申请日：2021-07-21
Inventor： Zhidong YUAN , Yongqian LI , Dacheng ZHANG , Jingbo XU , Can YUAN
IPC: G09G3/3233
CPC classification number: G09G3/3233 , G09G2300/0426 , G09G2300/0852 , G09G2330/021
Abstract: A display substrate includes an underlay substrate and a plurality of pixel unit groups. The plurality of pixel unit groups are located in a display region of the underlay substrate. At least one pixel unit group includes a plurality of sub-pixel groups, wherein at least one sub-pixel group includes a pixel circuit. The pixel circuit includes a first sub-pixel circuit, a second sub-pixel circuit, and a light emitting control sub-circuit. The first sub-pixel circuit and the second sub-pixel circuit are both electrically connected to the light emitting control sub-circuit. The light emitting control sub-circuit is configured to control a first light emitting element electrically connected to the first sub-pixel circuit to emit light, and to control a second light emitting element electrically connected to the second sub-pixel circuit to emit light.
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公开(公告)号：US20240138211A1
公开(公告)日：2024-04-25
申请号：US17926747
申请日：2021-11-29
Inventor： Zhidong YUAN , Yongqian LI , Can YUAN , Jun LIU
IPC: H10K59/131
CPC classification number: H10K59/131
Abstract: A display substrate and a display device are provided. The display substrate includes: a base substrate and a plurality of sub-pixels arranged on the base substrate, the plurality of the sub-pixels are arranged in an array, the sub-pixel includes: a reference signal line and a second scan line; and a sub-pixel driving circuit including a driving transistor and a second transistor, a gate electrode of the second transistor is coupled to the second scan line, a first electrode of the second transistor and the reference signal line form an integrated structure, a second electrode of the second transistor is coupled to a gate electrode of the driving transistor.
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公开(公告)号：US20230252943A1
公开(公告)日：2023-08-10
申请号：US17788627
申请日：2021-09-13
Inventor： Zhidong YUAN , Can YUAN , Yongqian LI , Lang LIU
IPC: G09G3/3233 , G09G3/3283
CPC classification number: G09G3/3233 , G09G3/3283 , G09G2320/0247 , G09G2300/0426 , G09G2310/08
Abstract: The present disclosure provides a display control method and a display control device. The display control method is used for a display panel. The display panel includes at least a first display area and a second display area arranged in a first direction, the first display area is coupled to a first signal line, and the second display area is coupled to a second signal line. The display control method includes: controlling a first sub-pixel in the first display area to display an image via the first signal line; and controlling a second sub-pixel in the second display area to display an image via the second signal line. A light-emission phase of the first sub-pixel at most partially overlaps a light-emission phase of the second sub-pixel.
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Patent Agency Ranking
公开(公告)号：US20230079091A1
公开(公告)日：2023-03-16
申请号：US17793536
申请日：2021-09-02
Inventor： Can YUAN , Yongqian LI , Zhidong YUAN
IPC: G09G3/32 , H03K17/693 , G09G3/3275
Abstract: A multiplexer circuit includes a first selection sub-circuit and a second selection sub-circuit. The first selection sub-circuit configured to transmit an input signal received at a input signal terminal to a first output terminal in response to a first control signal received at a first control terminal, and transmit a voltage of a power supply voltage terminal to the first output terminal in response to a second control signal received at a second control terminal. The second selection sub-circuit configured to transmit the input signal received at the input signal terminal to a second output terminal in response to a third control signal received at a third control terminal, and transmit the voltage of the power supply voltage terminal to the second output terminal in response to a fourth control signal received at a fourth control terminal.
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公开(公告)号：US20220359847A1
公开(公告)日：2022-11-10
申请号：US17635216
申请日：2021-04-21
Inventor： Can YUAN , Yongqian LI , Bin ZHOU , Ning LIU , Zhidong YUAN
Abstract: The present disclosure provides a display substrate, a manufacturing method thereof, and a display device. The display substrate includes a substrate, and a compensation electrode, an auxiliary electrode, a light-emitting functional layer, and a cathode layer arranged on one side of the substrate. The auxiliary electrode is arranged on one side of the compensation electrode away from the substrate, and coupled to the compensation electrode. A first notch is formed in a side surface of the auxiliary electrode, and at least a part of the first notch extends in a direction parallel to the substrate. The light-emitting functional layer is arranged on one side of the auxiliary electrode away from the substrate, and interrupted at the first notch. The cathode layer is arranged on one side of the light-emitting functional layer away from the substrate, and coupled to the auxiliary electrode at the first notch.
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公开(公告)号：US20220122533A1
公开(公告)日：2022-04-21
申请号：US17271914
申请日：2020-05-13
Inventor： Can YUAN , Pan XU , Yongqian LI , Zhidong YUAN
IPC: G09G3/3233
Abstract: Pixel driving method for driving pixel unit display driving method and display substrate are provided. The pixel unit includes pixel driving circuit, including driving transistor, storage capacitor, and data writing circuit, the driving transistor has control electrode coupled to first terminals of the data writing circuit and the storage capacitor, and first electrode coupled to second terminal of the storage capacitor, and second terminal of the data writing circuit is coupled to data line. The pixel driving method includes: loading a data voltage into the data line, and controlling the first and second terminals of the data writing circuit to be connected; controlling the data line to be floating, and maintaining connection between the first and second terminals of the data writing circuit to reduce gate-source voltage of the driving transistor; and controlling the first and second terminals of the data writing circuit to be disconnected.
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公开(公告)号：US20210384288A1
公开(公告)日：2021-12-09
申请号：US17287997
申请日：2020-08-07
Inventor： Meng LI , Yongqian LI , Zhidong YUAN , Can YUAN
IPC: H01L27/32
Abstract: A pixel structure includes: gate lines and data lines disposed crosswise and a plurality of pixel repetition modules distributed in an array. A pixel repetition module includes: a plurality of pixel units arranged in order, wherein each pixel unit includes three sub-pixels arranged in a triangular structure, and the three sub-pixels in each pixel unit and the three sub-pixels in an adjacent pixel unit are arranged inversely with respect to each other; each pixel unit corresponds to two groups of gate lines, wherein each group of gate lines includes two gate lines parallel to each other, a first group of gate lines are located on a first outer side and a second outer side of the pixel units respectively, and a second group of gate lines are both located between the sub-pixels located in a first row and the sub-pixels located in a second row in the pixel units.
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公开(公告)号：US20210335269A1
公开(公告)日：2021-10-28
申请号：US17206121
申请日：2021-03-19
Inventor： Zhidong YUAN , Pan XU , Yongqian LI , Can YUAN
IPC: G09G3/3266 , G09G3/3233 , G11C19/28
Abstract: The present disclosure relates to the field of display technology, and provides a shift register unit and a driving method thereof, a gate driving circuit, and a display panel. The shift register unit includes: an input circuit, a charging circuit, an inverter circuit, an output circuit, and a pull-down circuit. The input circuit is connected to a second clock signal terminal, a signal input terminal and a first node. The inverter circuit is connected to the signal input terminal, the second clock signal terminal, a first power supply terminal, a second power supply terminal and a pull-down node. The output circuit is connected to the pull-up node, the first power supply terminal and an output terminal. The pull-down circuit is connected to the pull-down node, the second power supply terminal, the pull-up node, and the output terminal.
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