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公开(公告)号：US20220149142A1
公开(公告)日：2022-05-12
申请号：US17584475
申请日：2022-01-26
Inventor： Yao Huang , Weiyun Huang , Yue Long , Chao Zeng , Meng Li
IPC: H01L27/32
Abstract: The present disclosure provides an array substrate and a display device. The array substrate includes: a sub-pixel, in a display region and including a light-emitting element, the light-emitting element including a first electrode, a light-emitting layer and a second electrode; a positive power line, connected to the first electrode; a positive power bus, connected to the positive power line; three positive power access ends, at a side of the positive power bus away from a display region, and respectively connected to the positive power bus; a negative power line; an auxiliary electrode, respectively connected to the negative power line and the second electrode; three negative power access ends, at the side of the positive power bus away from the display region, and respectively connected to the negative power line; and a negative power auxiliary line, respectively connected to the negative power access end and the auxiliary electrode.
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公开(公告)号：US20220115486A1
公开(公告)日：2022-04-14
申请号：US17279855
申请日：2020-05-19
Inventor： Zhidong Yuan , Dacheng Zhang , Yongqian Li , Lang Liu , Zhongyuan Wu , Can Yuan , Meng Li
Abstract: A display substrate includes: a base substrate including a display area and a peripheral area pixel units in the display area, each including a pixel drive circuit and a light emitting device the light emitting device including a first electrode, a second electrode, and a light emitting layer; a first power trace located in the peripheral area and electrically connected to the first electrode; a second power trace located in the peripheral area and electrically connected to the second electrode; a planarization layer with at least a portion thereof being located in the peripheral area. An orthographic projection of the planarization layer on the base substrate at least partially overlaps an orthographic projection of each of the first and second power traces on the base substrate, the first and second power traces are located in different layers, and a portion of the planarization layer is located between the first and second power traces.
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公开(公告)号：US20220013610A1
公开(公告)日：2022-01-13
申请号：US17280316
申请日：2020-05-15
Inventor： Meng Li , Zhongyuan Wu , Yongqian Li , Dacheng Zhang , Jingquan Wang , Yu Wang , Chen Xu
IPC: H01L27/32 , G09G3/3225
Abstract: The present disclosure provides a display panel and an electronic device. The display panel includes: a base substrate; and a pixel arranged on the base substrate, wherein the pixel includes a first sub-pixel including a first sub-pixel drive circuit and a first light emitting element and a second sub-pixel including a second sub-pixel drive circuit and a second light emitting element, the first and second sub-pixel drive circuits are arranged sequentially in a first direction and extend in a second direction, wherein the first light emitting element includes a first anode, the second light emitting element includes a second anode, an orthographic projection of each of the first and the second anodes partially covers an orthographic projections of the first and second sub-pixel drive circuits, and the orthographic projection of the first anode does not overlap the orthographic projection of the second anode.
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公开(公告)号：US11222565B2
公开(公告)日：2022-01-11
申请号：US16072049
申请日：2018-01-08
Inventor： Xuehuan Feng , Xing Zhang , Qi Hu , Pan Xu , Yongqian Li , Meng Li , Zhidong Yuan , Zhenfei Cai , Can Yuan
Abstract: The present application discloses a shift register, a gate driving circuit and a driving method thereof, and a display apparatus. The shift register includes an input sub-circuit, an output sub-circuit, a reset control sub-circuit, a pull-up node reset sub-circuit, and an output signal reset sub-circuit; the input sub-circuit is configured to pre-charge the pull-up node under the control of a signal input to the first signal input terminal; the output sub-circuit is configured to output, through the signal output terminal, a signal input to the first clock signal input terminal under the control of a potential of the pull-up node; the reset control sub-circuit is configured to control, under the control of a reset signal input to the second signal input terminal, whether the pull-up node reset sub-circuit and the output signal reset sub-circuit operate to reset the pull-up node and the signal output terminal, respectively.
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公开(公告)号：US20210399073A1
公开(公告)日：2021-12-23
申请号：US17270596
申请日：2020-05-15
Abstract: The present disclosure provides a display panel and an electronic device. The display panel includes: a base substrate; a pixel arranged on the base substrate, wherein the pixel includes a plurality of sub-pixel drive circuits sequentially arranged in the first direction in the display area, each of the sub-pixel drive circuits includes a switching transistor, a detection transistor and a storage capacitor, the switching transistor and the detection transistor are respectively located on both sides of the storage capacitor in a second direction; a first gate line configured to provide a first scanning signal to the plurality of sub-pixel drive circuits; and a second gate line configured to provide a second scanning signal to the plurality of sub-pixel drive circuits.
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Patent Agency Ranking
公开(公告)号：US20210367025A1
公开(公告)日：2021-11-25
申请号：US17256197
申请日：2019-11-15
Inventor： Yao Huang , Weiyun Huang , Yue Long , Chao Zeng , Meng Li
IPC: H01L27/32
Abstract: The present disclosure provides an array substrate and a display device. The array substrate includes: a sub-pixel, in a display region and including a light-emitting element, the light-emitting element including a first electrode, a light-emitting layer and a second electrode; a positive power line, connected to the first electrode; a positive power bus, connected to the positive power line; three positive power access ends, at a side of the positive power bus away from a display region, and respectively connected to the positive power bus; a negative power line; an auxiliary electrode, respectively connected to the negative power line and the second electrode; three negative power access ends, at the side of the positive power bus away from the display region, and respectively connected to the negative power line; and a negative power auxiliary line, respectively connected to the negative power access end and the auxiliary electrode.
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公开(公告)号：US20210134223A1
公开(公告)日：2021-05-06
申请号：US16639116
申请日：2019-09-27
Inventor： Meng Li
IPC: G09G3/3258 , G09G3/3266 , G09G3/3291
Abstract: An array substrate is provided. The array substrate includes a plurality of pixel groups, a respective one of the plurality of pixel groups including two adjacent pixels in a same row of pixels, a respective one of the two adjacent pixels including three subpixels; a plurality of scanning line groups configured to respectively control a plurality of rows of pixels, a respective one group of the plurality of scanning line groups including four scanning lines; and a plurality of data line groups respectively connected to a plurality of columns of pixel groups of the plurality of pixel groups, a respective one group of the plurality of data line groups including three data lines. The two adjacent pixels includes a first pixel and a second pixel. Each of the first pixel and the second pixel includes a first subpixel, a second subpixel, and a third subpixel.
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公开(公告)号：US20200211435A1
公开(公告)日：2020-07-02
申请号：US16546470
申请日：2019-08-21
Inventor： Ying Wang , Meng Li , Hongmin Li
Abstract: Provided are a shift register unit, a driving method, a gate drive circuit and a display device in the field of display technology. The shift register unit includes an input circuit, an output circuit, and a first pull-down circuit. The output circuit is coupled to a first clock signal terminal, a first node, a first DC power supply terminal, and a first output terminal respectively, and configured to output a first power supply signal from the first DC power supply terminal to the first output terminal in response to a potential of the first node and a first clock signal provided by the first clock signal terminal.
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公开(公告)号：US20190206352A1
公开(公告)日：2019-07-04
申请号：US16008698
申请日：2018-06-14
Inventor： Ying Wang , Meng Li , Xun Pu , Hongmin Li
Abstract: Embodiments of the present disclosure provide a shift register and a driving method thereof and a gate driving circuit. The shift register comprises an inputting circuit, a first outputting circuit, and a second outputting circuit. The first outputting circuit may comprise a first pulling-up sub-circuit, a first outputting sub-circuit, a first pulling-down sub-circuit, and a switching sub-circuit. A controlling terminal of switching sub-circuit is coupled to a controlling terminal of the first pulling-up sub-circuit. An inputting terminal of the switching sub-circuit is coupled to the outputting terminal of a first outputting sub-circuit. The second outputting circuit may comprise a second pulling-up sub-circuit, a second outputting sub-circuit, and a second pulling-down sub-circuit. An inputting terminal of the second pulling-up sub-circuit is coupled to an outputting terminal of the switching sub-circuit. A controlling terminal of the second outputting sub-circuit is coupled to an outputting terminal of the second pulling-up sub-circuit.
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公开(公告)号：US12217672B2
公开(公告)日：2025-02-04
申请号：US17772288
申请日：2021-05-20
Inventor： Yao Huang , Binyan Wang , Meng Li
IPC: G09G3/3233
Abstract: A pixel circuit and a driving method thereof, a display substrate and a display device are provided. The pixel circuit includes a driving sub-circuit, a first switch sub-circuit and a first light-emitting control sub-circuit. The driving sub-circuit includes a control terminal connected with a first node, a first terminal connected with a second node and a second terminal connected with a third node, and is configured to control a driving signal from the first node to the third node for driving a light-emitting element; the first switch sub-circuit is configured to control conduction of the driving signal between the third node and a fourth node; the first light-emitting control sub-circuit is connected with a first electrode of the light-emitting element through a fifth node, and is configured to control conduction of the driving signal between the fourth node and the fifth node.
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