公开(公告)号：US07634713B1

公开(公告)日：2009-12-15

申请号：US11435467

申请日：2006-05-16

申请人： Ninh D. Ngo

发明人： Ninh D. Ngo

IPC分类号： H03M13/00 ,  G11C29/00 ,  G01R31/28

CPC分类号： H03M13/091 ,  G01R31/31816 ,  G01R31/318533 ,  G11C2029/0401 ,  G11C2029/0411 ,  H03K19/17764

摘要： Error detection and error location determination circuitry is provided for detecting and locating soft errors in random-access-memory arrays on programmable integrated circuits. The random-access-memory arrays contain rows and columns of random-access-memory cells. Some of the cells are loaded with configuration data and produce static output signals that are used to program associated regions of programmable logic. Cyclic redundancy check error correction check bits are computed for each column of each array. The error correction check bits are stored in corresponding columns of cells in the array. During normal operation of an integrated circuit in a system, the cells are subject to soft errors caused by background radiation strikes. The error detection and error location determination circuitry contains linear feedback shift register circuitry that processes columns of array data. The circuitry continuously processes the data to identify the row and column location of each error.

摘要翻译： 提供错误检测和错误位置确定电路，用于检测和定位可编程集成电路上的随机存取存储器阵列中的软错误。 随机存取存储器阵列包含随机访问存储器单元的行和列。 一些单元载入配置数据，并产生用于编程可编程逻辑的相关区域的静态输出信号。 对每个阵列的每列计算循环冗余校验错误校正位。 纠错校验位存储在阵列中相应的单元格列中。 在系统中的集成电路的正常操作期间，单元受到由背景辐射引起的软错误。 误差检测和误差位置确定电路包含处理阵列数据列的线性反馈移位寄存器电路。 电路连续处理数据以识别每个错误的行和列位置。

公开(公告)号：US20090282306A1

公开(公告)日：2009-11-12

申请号：US12503637

申请日：2009-07-15

申请人： Ninh D. Ngo ,  Andy L. Lee ,  Kerry Veenstra

发明人： Ninh D. Ngo ,  Andy L. Lee ,  Kerry Veenstra

IPC分类号： G01R31/28

CPC分类号： H03K19/17764 ,  G06F11/1004

摘要： Error detection circuitry is provided on a programmable logic resource. Programmable logic resource configuration data is loaded into a cyclic redundancy check (CRC) module where a checksum calculation may be performed. In one embodiment, the checksum may be compared to an expected value, which is a precomputed checksum on data prior to being programmed into or while data is being programmed into a programmable logic resource. In another embodiment, the expected value may be included in the checksum calculation. An output indicating whether an error is detected may be generated depending on the relationship between the checksum and the expected value, or on the value of the checksum. This output may be sent to an output pin that is accessible by user logic.

摘要翻译： 在可编程逻辑资源上提供错误检测电路。 可编程逻辑资源配置数据被加载到可以执行校验和计算的循环冗余校验（CRC）模块中。 在一个实施例中，校验和可以与预期值进行比较，期望值是在被编程到数据被编程到可编程逻辑资源之前或数据被编程到数据之前的预计算校验和。 在另一个实施例中，期望值可以包括在校验和计算中。 可以根据校验和和期望值之间的关系或校验和的值来生成指示是否检测到错误的输出。 该输出可以被发送到用户逻辑可访问的输出引脚。

公开(公告)号：US07577055B2

公开(公告)日：2009-08-18

申请号：US11930739

申请日：2007-10-31

申请人： Ninh D. Ngo ,  Andy L. Lee ,  Kerry Veenstra

发明人： Ninh D. Ngo ,  Andy L. Lee ,  Kerry Veenstra

IPC分类号： G11C8/00 ,  G01C31/28

CPC分类号： H03K19/17764 ,  G06F11/1004

摘要： Error detection circuitry is provided on a programmable logic resource. Programmable logic resource configuration data is loaded into a cyclic redundancy check (CRC) module where a checksum calculation may be performed. In one embodiment, the checksum may be compared to an expected value, which is a precomputed checksum on data prior to being programmed into or while data is being programmed into a programmable logic resource. In another embodiment, the expected value may be included in the checksum calculation. An output indicating whether an error is detected may be generated depending on the relationship between the checksum and the expected value, or on the value of the checksum. This output may be sent to an output pin that is accessible by user logic.

摘要翻译： 在可编程逻辑资源上提供错误检测电路。 可编程逻辑资源配置数据被加载到可以执行校验和计算的循环冗余校验（CRC）模块中。 在一个实施例中，校验和可以与预期值进行比较，期望值是在被编程到数据被编程到可编程逻辑资源之前或数据被编程到数据之前的预计算校验和。 在另一个实施例中，期望值可以包括在校验和计算中。 可以根据校验和和期望值之间的关系或校验和的值来生成指示是否检测到错误的输出。 该输出可以被发送到用户逻辑可访问的输出引脚。