公开(公告)号：US06754804B1

公开(公告)日：2004-06-22

申请号：US09753239

申请日：2000-12-29

申请人： Lawrence Henry Hudepohl ,  Darren Miller Jones ,  Radhika Thekkath ,  Franz Treue

发明人： Lawrence Henry Hudepohl ,  Darren Miller Jones ,  Radhika Thekkath ,  Franz Treue

IPC分类号： G06F1516

CPC分类号： G06F9/3853 ,  G06F9/3879 ,  G06F9/3885

摘要： A configurable coprocessor interface between a central processing unit (CPU) and a coprocessor is provided. The interface groups signals that together comprises all the necessary information for a coprocessor to issue and execute instructions. Multiple issue groups are formed where each group supports different types of instructions, such as arithmetic instructions, or data transfer instructions. The coprocessor interface has an instruction transfer signal group for transferring different instructions from the CPU to the multi-issue coprocessor, sequentially or in parallel, an issue group designator for specifying an issue path within the multi-issue coprocessor for execution of the instructions, a busy signal group, for allowing the coprocessor to signal the CPU that it cannot receive a transfer of one or more of the different instructions, and an instruction order signal group for indicating to the coprocessor a relative execution order for multiple instructions that are transferred in parallel.

摘要翻译： 提供了中央处理单元（CPU）和协处理器之间的可配置协处理器接口。 接口组信号一起包括协处理器发出和执行指令的所有必要信息。 形成多个问题组，其中每个组支持不同类型的指令，例如算术指令或数据传输指令。 协处理器接口具有指令传送信号组，用于将不同的指令从CPU传送到多问题协处理器，顺序或并行，用于指定用于执行指令的多问题协处理器内的发布路径的问题组指示符， 忙信号组，用于允许协处理器向CPU发信号通知其不能接收一个或多个不同指令的传输，以及用于向协处理器指示并行传送的多个指令的相对执行顺序的指令顺序信号组 。