公开(公告)号：US20130067284A1

公开(公告)日：2013-03-14

申请号：US13609047

申请日：2012-09-10

申请人： Thomas Benjamin Berg ,  Ryan C. Kinter ,  Jaidev Prasad Patwardhan ,  Radhika Thekkath

发明人： Thomas Benjamin Berg ,  Ryan C. Kinter ,  Jaidev Prasad Patwardhan ,  Radhika Thekkath

IPC分类号： G06F11/26

CPC分类号： G06F11/3636 ,  G06F12/0815

摘要： A method of coordinating trace information in a multiprocessor system includes receiving processor trace information from a set of processors. The processor trace information from each processor includes a processor identity and a coherence indicator that demarks selective shared memory transactions. Coherence manager trace information is generated for each of the processors. The coherence manager trace information for each processor includes trace metrics and a coherence indicator.

摘要翻译： 在多处理器系统中协调跟踪信息的方法包括从一组处理器接收处理器跟踪信息。 来自每个处理器的处理器跟踪信息包括处理器标识和相干指示符，其指示选择性共享存储器事务。 为每个处理器生成一致性管理器跟踪信息。 每个处理器的相干管理器跟踪信息包括跟踪量度和一致性指标。

公开(公告)号：US07548996B2

公开(公告)日：2009-06-16

申请号：US11224738

申请日：2005-09-12

申请人： David Baker ,  Christopher Basoglu ,  Benjamin Cutler ,  Gregorio Gervasio ,  Woobin Lee ,  Yatin Mundkur ,  Toru Nojiri ,  John O'Donnell ,  John Poole, legal representative ,  Ashok Raman ,  Eric Rehm ,  Radhika Thekkath

发明人： David Poole

IPC分类号： G06F13/28

CPC分类号： G06F13/30 ,  G06F13/1605

摘要： In an information processing system which has plurality of modules including a processor, a main memory and a plurality of I/O devices, a data transfer switch for performing data transfer operations between the processor, main memory and I/O devices comprises a request bus which has a request bus arbiter for receiving read and write requests from each one of the plurality of modules. A processor memory bus is configured to receive address and data information from a predetermined number of modules, including the processor. The processor memory bus has a data bus arbiter for receiving data read and write requests from each one of the predetermined number of modules which are coupled to the processor memory bus.An internal memory bus is configured to receive address and data information from a predetermined number of modules, including the memory and the I/O devices. The internal memory bus has a data bus arbiter for receiving data read and write requests from each one of the predetermined number of modules coupled to the internal memory bus. A transceiver system is coupled to the processor memory bus and the internal memory bus for transferring data between the processor memory bus and the internal memory bus.

摘要翻译： 在具有处理器，主存储器和多个I / O设备的多个模块的信息处理系统中，用于在处理器，主存储器和I / O设备之间执行数据传送操作的数据传送开关包括请求总线 其具有用于从多个模块中的每一个接收读取和写入请求的请求总线仲裁器。 处理器存储器总线被配置为从包括处理器的预定数量的模块接收地址和数据信息。 处理器存储器总线具有用于从耦合到处理器存储器总线的预定数量的模块中的每一个接收数据读取和写入请求的数据总线仲裁器。 内部存储器总线被配置为从包括存储器和I / O设备的预定数量的模块接收地址和数据信息。 内部存储器总线具有用于从耦合到内部存储器总线的预定数量的模块中的每一个接收数据读取和写入请求的数据总线仲裁器。 收发器系统耦合到处理器存储器总线和内部存储器总线，用于在处理器存储器总线和内部存储器总线之间传送数据。

公开(公告)号：US20090037704A1

公开(公告)日：2009-02-05

申请号：US12187631

申请日：2008-08-07

申请人： Radhika Thekkath

发明人： Radhika Thekkath

IPC分类号： G06F9/30

CPC分类号： G06F11/3636

摘要： A system and method for program counter and data tracing is disclosed. The tracing mechanism of the present invention enables increased visibility into the hardware and software state of the processor core.

摘要翻译： 公开了一种用于程序计数器和数据跟踪的系统和方法。 本发明的跟踪机制能够提高对处理器核心的硬件和软件状态的可见性。

公开(公告)号：US20080082801A1

公开(公告)日：2008-04-03

申请号：US11537574

申请日：2006-09-29

申请人： Ernest L. EDGAR ,  Radhika Thekkath

发明人： Ernest L. EDGAR ,  Radhika Thekkath

IPC分类号： G06F9/44

CPC分类号： G06F11/3636 ,  G06F11/3648

摘要： A method of tracing processor instructions includes characterizing processor state changes in accordance with simplified instruction state descriptors. The simplified instruction state descriptors are then traced with processor instructions, but processor data is not traced.

摘要翻译： 跟踪处理器指令的方法包括根据简化的指令状态描述符表征处理器状态变化。 然后，使用处理器指令跟踪简化的指令状态描述符，但不跟踪处理器数据。

公开(公告)号：US07315937B2

公开(公告)日：2008-01-01

申请号：US10956490

申请日：2004-10-01

申请人： Darren M. Jones ,  Ryan C. Kinter ,  Rivka Shenhav ,  Radhika Thekkath

发明人： Darren M. Jones ,  Ryan C. Kinter ,  Rivka Shenhav ,  Radhika Thekkath

IPC分类号： G06F7/76

CPC分类号： G06F9/30018 ,  G06F9/30032

摘要： A method of extracting bits of a bit stream including retrieving bits from the bit stream into an accumulator, specifying a size value specifying a number of bits to extract, storing a position value into a control register, and executing a bit extraction instruction. The bit extraction instruction includes copying the size value number of bits from the accumulator beginning at the position value into a target register, setting any remaining bits of the target register to zero, and decrementing the position value by an amount based on the size value. The method may include loading bits from a bit stream into a register and moving the contents of the register into the accumulator to replenish the accumulator. The method may include determining, based on the position value, whether the accumulator needs to be replenished, and if not, branching to bypass replenishing functions.

摘要翻译： 提取比特流的比特的方法，包括从比特流中检索比特到累加器中，指定指定要提取的比特数的大小值，将位置值存储到控制寄存器中，以及执行比特提取指令。 比特提取指令包括将来自累加器的位置值开始的大小值比特数复制到目标寄存器中，将目标寄存器的任何剩余比特设置为零，并且基于大小值递减位置值。 该方法可以包括将比特流加载到寄存器中并将寄存器的内容移动到累加器中以补充累加器。 该方法可以包括基于位置值确定累加器是否需要被补充，如果不是，则分支到旁路补充功能。

公开(公告)号：US20070174598A1

公开(公告)日：2007-07-26

申请号：US11336923

申请日：2006-01-23

申请人： Radhika Thekkath ,  Georgi Beloev

发明人： Radhika Thekkath ,  Georgi Beloev

IPC分类号： G06F9/44

CPC分类号： G06F9/3004 ,  G06F9/30043 ,  G06F9/30098 ,  G06F9/35 ,  G06F9/384

摘要： A RISC processor having a data moving engine and instructions that associate register addresses with memory addresses. In an embodiment, the instructions include a read-tie instruction, a single write-tie instruction, a dual write-tie instruction, and an untie instruction. The read-tie, single write-tie, and dual write-tie instructions are used to associate software accessible register addresses with memory addresses. These associations effect the operation of the data moving engine such that, for the duration of the associations, the data moving engine routes data to and from associated memory addresses and the execution unit of the processor in response to instructions that specify moving data to and from the associated register addresses. The invention reduces the number of instructions and hardware overhead associated with implementing program loops in a RISC processor.

摘要翻译： 具有数据移动引擎的RISC处理器和将寄存器地址与存储器地址相关联的指令。 在一个实施例中，指令包括读取连接指令，单个写入指令，双重写入指令和解开指令。 读带，单写和双写指令用于将软件可访问寄存器地址与存储器地址相关联。 这些关联影响数据移动引擎的操作，使得在关联期间，数据移动引擎响应于指定移动数据到和从...移动数据的指令，将数据路由到相关联的存储器地址和处理器的执行单元 关联的寄存器地址。 本发明减少了与RISC处理器中实现程序循环相关联的指令数量和硬件开销。

公开(公告)号：US07237090B1

公开(公告)日：2007-06-26

申请号：US09751747

申请日：2000-12-29

申请人： Lawrence Henry Hudepohl ,  Darren Miller Jones ,  Radhika Thekkath ,  Franz Treue

发明人： Lawrence Henry Hudepohl ,  Darren Miller Jones ,  Radhika Thekkath ,  Franz Treue

IPC分类号： G06F13/14

CPC分类号： G06F9/3824 ,  G06F9/3802 ,  G06F9/3836 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3859 ,  G06F9/3885

摘要： An interface for transferring data between a central processing unit (CPU) and a plurality of coprocessors is provided. The interface includes an instruction bus and a data bus. The instruction bus is configured to transfer instructions to the plurality of coprocessors in an instruction transfer order, where particular instructions designate and direct one of the plurality of coprocessors to transfer the data to/from the CPU. The data bus is configured to subsequently transfer the data. Data order signals within the data bus prescribe a data transfer order that differs from the instruction transfer order by prescribing a transfer corresponding to a specific outstanding particular instruction, where the data transfer order is relative to outstanding instructions. The outstanding instructions are those of the particular instructions transferred to the one of the plurality of coprocessors that have not completed a data transfer.

摘要翻译： 提供了用于在中央处理单元（CPU）和多个协处理器之间传送数据的接口。 接口包括指令总线和数据总线。 指令总线被配置为以指令传送顺序将指令传送到多个协处理器，其中特定指令指示并引导多个协处理器中的一个将数据传送到/从CPU传送数据。 数据总线被配置为随后传送数据。 数据总线内的数据顺序信号通过规定与特定未完成特定指令相对应的传输，指定与指令传输顺序不同的数据传输顺序，其中数据传输顺序相对于未完成的指令。 未完成的指令是传送到尚未完成数据传送的多个协处理器之一的特定指令的指令。

公开(公告)号：US20070089095A1

公开(公告)日：2007-04-19

申请号：US11608725

申请日：2006-12-08

申请人： Radhika Thekkath ,  Franz Treue ,  Soren Kragh ,  Vidya Rajagopalan

发明人： Radhika Thekkath ,  Franz Treue ,  Soren Kragh ,  Vidya Rajagopalan

IPC分类号： G06F9/44

CPC分类号： G06F9/3836 ,  G06F9/3855 ,  G06F9/3857 ,  G06F11/3636

摘要： A system and method for program counter and data tracing in a multi-issue processor is disclosed. Instructions are traced in program sequence order. In one embodiment instructions are traced in graduation order from a reorder buffer. The tracing mechanism of the present invention enables increased visibility into the hardware and software state of the processor core.

摘要翻译： 公开了一种用于多问题处理器中的程序计数器和数据跟踪的系统和方法。 说明以程序顺序排列。 在一个实施例中，以重排序缓冲器的顺序追踪指令。 本发明的跟踪机制能够提高对处理器核心的硬件和软件状态的可见性。

公开(公告)号：US07065675B1

公开(公告)日：2006-06-20

申请号：US09850195

申请日：2001-05-08

申请人： Radhika Thekkath ,  Scott Michael McCoy ,  Franz Treue ,  Morten Zilmer ,  G. Michael Uhler

发明人： Radhika Thekkath ,  Scott Michael McCoy ,  Franz Treue ,  Morten Zilmer ,  G. Michael Uhler

IPC分类号： G06F11/00

CPC分类号： G01R31/318544 ,  G01R31/31705

摘要： A system and method for providing efficient block transfer operations through a test access port uses a Fastdata register. The Fastdata register, in part, emulates a pending process access bit (“PrAcc”) typically found in a Control register associated with the test access port. When a Fastdata access (either a Fastdata upload or a Fastdata download) is requested by a probe coupled to the test access port, the Fastdata register is serially coupled to a data register also associated with the test access port. With these registers so coupled and through the operation of the Fastdata register, downloading and uploading data can be accomplished using a single register operation.

摘要翻译： 通过测试访问端口提供有效的块传输操作的系统和方法使用Fastdata寄存器。 Fastdata寄存器部分地模拟通常在与测试访问端口相关联的控制寄存器中找到的待处理进程访问位（“PrAcc”）。 当FastData访问（Fastdata上传或Fastdata下载）被耦合到测试访问端口的探测器请求时，Fastdata寄存器串行耦合到也与测试访问端口相关联的数据寄存器。 通过这些寄存器如此耦合，并通过Fastdata寄存器的操作，可以使用单个寄存器操作来完成下载和上传数据。

公开(公告)号：US20060101258A1

公开(公告)日：2006-05-11

申请号：US10956490

申请日：2004-10-01

申请人： Darren Jones ,  Ryan Kinter ,  Rivka Shenhav ,  Radhika Thekkath

发明人： Darren Jones ,  Ryan Kinter ,  Rivka Shenhav ,  Radhika Thekkath

IPC分类号： G06F7/24

CPC分类号： G06F9/30018 ,  G06F9/30032

摘要： A method of extracting bits of a bit stream including retrieving bits from the bit stream into an accumulator, specifying a size value specifying a number of bits to extract, storing a position value into a control register, and executing a bit extraction instruction. The bit extraction instruction includes copying the size value number of bits from the accumulator beginning at the position value into a target register, setting any remaining bits of the target register to zero, and decrementing the position value by an amount based on the size value. The method may include loading bits from a bit stream into a register and moving the contents of the register into the accumulator to replenish the accumulator. The method may include determining, based on the position value, whether the accumulator needs to be replenished, and if not, branching to bypass replenishing functions.

摘要翻译： 提取比特流的比特的方法，包括从比特流中检索比特到累加器中，指定指定要提取的比特数的大小值，将位置值存储到控制寄存器中，以及执行比特提取指令。 比特提取指令包括将来自累加器的位置值开始的大小值比特数复制到目标寄存器中，将目标寄存器的任何剩余比特设置为零，并且基于大小值递减位置值。 该方法可以包括将比特流加载到寄存器中并将寄存器的内容移动到累加器中以补充累加器。 该方法可以包括基于位置值确定累加器是否需要被补充，如果不是，则分支到旁路补充功能。