公开(公告)号：US08942055B2

公开(公告)日：2015-01-27

申请号：US13765384

申请日：2013-02-12

申请人： Annie-Li-Keow Lum ,  Kuoyuan (Peter) Hsu

发明人： Annie-Li-Keow Lum ,  Kuoyuan (Peter) Hsu

IPC分类号： G11C5/14

CPC分类号： G11C11/419

摘要： A circuit includes a voltage generating circuit and a voltage keeper circuit. The voltage generating circuit includes a first node. The voltage keeper circuit includes a second node and a third node. The first node is coupled with the second node. The voltage generating circuit is configured to generate a voltage value at the first node and the second node to maintain the third node at a particular third node voltage.

摘要翻译： 电路包括电压产生电路和电压保持器电路。 电压产生电路包括第一节点。 电压保持器电路包括第二节点和第三节点。 第一节点与第二节点耦合。 电压产生电路被配置为在第一节点和第二节点处产生电压值，以将第三节点维持在特定的第三节点电压。

公开(公告)号：US07656698B1

公开(公告)日：2010-02-02

申请号：US11656650

申请日：2007-01-23

申请人： Pavel Poplevine ,  Annie-Li-Keow Lum ,  Hengyang (James) Lin ,  Andrew J. Franklin

发明人： Pavel Poplevine ,  Annie-Li-Keow Lum ,  Hengyang (James) Lin ,  Andrew J. Franklin

IPC分类号： G11C11/00

CPC分类号： G11C14/0063 ,  G11C16/0441

摘要： A 4-transistor non-volatile memory (NVM) cell includes a static random access memory (SRAM) cell structure. The NVM cell utilizes a reverse Fowler-Nordheim tunneling programming technique that, in combination with the SRAM cell structure, allows an entire array to be programmed at one cycle. Equalize transistors are utilized to obtain more uniform voltage on the floating gates after an erase operation. Utilization of decoupling pas gates during a read operation results in more charge difference on floating gates of programmed and erased cells.

摘要翻译： 4晶体管非易失性存储器（NVM）单元包括静态随机存取存储器（SRAM）单元结构。 NVM单元采用反向Fowler-Nordheim隧道编程技术，其结合SRAM单元结构允许在一个周期对整个阵列进行编程。 利用均衡晶体管在擦除操作之后在浮动栅极上获得更均匀的电压。 在读取操作期间使用去耦pas门导致编程和擦除单元的浮动栅极上的更多的电荷差异。

公开(公告)号：US20090129162A1

公开(公告)日：2009-05-21

申请号：US12284890

申请日：2008-09-25

申请人： Pavel Poplevine ,  Annie-Li-Keow Lum ,  Andrew Cao ,  Ernes Ho

发明人： Pavel Poplevine ,  Annie-Li-Keow Lum ,  Andrew Cao ,  Ernes Ho

IPC分类号： G11C16/04 ,  G11C16/06 ,  H01L21/336

CPC分类号： G11C14/00

摘要： A method of making a non-volatile memory (NVM) cell structure comprises the formation of a first NVM cell, a second NVM cell and an SRAM cell that includes first and second data nodes. A first pass gate structure is connected between the first NVM cell and the first data node of the SRAM cell, the first pass gate structure being responsive to first and second states of a first pass gate signal to respectively couple and decouple the first NVM cell and the SRAM cell. A first equalize structure is formed to connect the first pass gate structure and the first NVM cell and is responsive to a first equalize signal to connect the first NVM cell to ground. A second pass gate structure is connected between the second NVM cell and the second data node of the SRAM cell, the second pass gate structure being responsive to first and second states of a second pass gate signal to respectively couple and decouple the second NVM cell and the SRAM cell. A second equalize structure is connected between the second pass gate structure and the second NVM cell, the second equalize structure being responsive to a second equalize signal to connect the second NVM cell to ground. Appropriate biasing conditions are applied to the NVM cell structure to implement program/operations.

摘要翻译： 制造非易失性存储器（NVM）单元结构的方法包括形成包括第一和第二数据节点的第一NVM单元，第二NVM单元和SRAM单元。 第一通道栅极结构连接在第一NVM单元和SRAM单元的第一数据节点之间，第一通道栅极结构响应于第一和第二状态的第一通道栅极信号以分别耦合和去耦合第一NVM单元，以及 SRAM单元。 形成第一均衡结构以连接第一通道栅极结构和第一NVM单元，并且响应于第一均衡信号将第一NVM单元连接到地。 第二通路栅极结构连接在第二NVM单元和SRAM单元的第二数据节点之间，第二通道栅极结构响应第二通路栅极信号的第一和第二状态，以分别耦合和去耦合第二NVM单元，以及 SRAM单元。 第二均衡结构连接在第二通路栅极结构和第二NVM单元之间，第二均衡结构响应于第二均衡信号将第二NVM单元连接到地。 将适当的偏置条件应用于NVM单元结构以实现程序/操作。