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公开(公告)号：US20190393899A1
公开(公告)日：2019-12-26
申请号：US16559482
申请日：2019-09-03
Inventor： Sung-Ik PARK , Sun-Hyoung KWON , Heung-Mook KIM , Jae-Young LEE , Nam-Ho HUR
Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 2/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 256-symbol mapping.
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公开(公告)号：US20190393895A1
公开(公告)日：2019-12-26
申请号：US16560891
申请日：2019-09-04
Inventor： Sung-Ik PARK , Sun-Hyoung KWON , Jae-Young LEE , Heung-Mook KIM , Nam-Ho HUR
IPC: H03M13/11
Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 2/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 4096-symbol mapping.
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23.发明申请公开(公告)号：US20190356414A1
公开(公告)日：2019-11-21
申请号：US16529502
申请日：2019-08-01
Inventor： Sung-Ik PARK , Heung-Mook KIM , Sun-Hyoung KWON , Nam-Ho HUR
Abstract: A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword. The second memory is initialized to 0. The processor generates the LDPC codeword by performing accumulation with respect to the second memory using information bits. The accumulation is performed at parity bit addresses that are updated using a sequence corresponding to a parity check matrix (PCM).
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公开(公告)号：US20190356332A1
公开(公告)日：2019-11-21
申请号：US16526678
申请日：2019-07-30
Inventor： Sung-Ik PARK , Sun-Hyoung KWON , Jae-Young LEE , Heung-Mook KIM , Nam-Ho HUR
Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 3/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 1024-symbol mapping.
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25.发明申请公开(公告)号：US20190342032A1
公开(公告)日：2019-11-07
申请号：US16515760
申请日：2019-07-18
Inventor： Nam-Ho HUR , Sun-Hyoung KWON , Sung-Ik PARK , Heung-Mook KIM , Jae-Young LEE
Abstract: An apparatus and method for multiplexing signals using layered division multiplexing are disclosed. A signal multiplexing apparatus according to an embodiment of the present invention includes a combiner configured to combine a core layer signal and an enhanced layer signal at different power levels to generate a multiplexed signal, a power normalizer configured to reduce power of the multiplexed signal to power corresponding to the core layer signal, and a time interleaver configured to perform interleaving applied to both the core layer signal and the enhanced layer signal.
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Patent Agency Ranking
26.发明申请公开(公告)号：US20190260509A1
公开(公告)日：2019-08-22
申请号：US16401026
申请日：2019-05-01
Inventor： Sung-Ik PARK , Sun-Hyoung KWON , Jae-Young LEE , Bo-Mi LIM , Heung-Mook KIM , Nam-Ho HUR
Abstract: An apparatus and method for generating a broadcast signal frame for signaling a time interleaving mode are disclosed. An apparatus for generating broadcast signal frame according to an embodiment of the present invention includes a combiner configured to generate a multiplexed signal by combining a core layer signal and an enhanced layer signal; a power normalizer configured to perform power-normalizing for reducing the power of the multiplexed signal to a power level corresponding to the core layer signal; a time interleaver configured to generate a time-interleaved signal by performing time interleaving after performing the power-normalizing; and a frame builder configured to generate a broadcast signal frame including a preamble for signaling a time interleaving mode corresponding to the time interleaver for each of physical layer pipes (PLPs).
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公开(公告)号：US20190253076A1
公开(公告)日：2019-08-15
申请号：US16397557
申请日：2019-04-29
Inventor： Sung-Ik PARK , Sun-Hyoung KWON , Bo-Mi LIM , Jae-Young LEE , Heung-Mook KIM , Nam-Ho HUR
CPC classification number: H03M13/1102 , G06F11/1076 , H03M13/116 , H03M13/1185 , H03M13/255 , H03M13/2778
Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 3/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for quadrature phase shift keying (QPSK) modulation.
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公开(公告)号：US20190222233A1
公开(公告)日：2019-07-18
申请号：US16365533
申请日：2019-03-26
Inventor： Sung-Ik PARK , Sun-Hyoung KWON , Jae-Young LEE , Heung-Mook KIM , Nam-Ho HUR
CPC classification number: H03M13/2792 , G06F11/1012 , G06F11/1076 , G11B20/1806 , G11B20/1809 , G11B2020/185 , H03M13/1102 , H03M13/1165 , H03M13/255 , H03M13/27 , H03M13/2778
Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 3/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 4096-symbol mapping.
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公开(公告)号：US20190207629A1
公开(公告)日：2019-07-04
申请号：US16282229
申请日：2019-02-21
Inventor： Sung-Ik PARK , Heung-Mook KIM , Sun-Hyoung KWON , Nam-Ho HUR
CPC classification number: H03M13/255 , H03M13/036 , H03M13/1102 , H03M13/1105 , H03M13/116 , H03M13/1165 , H03M13/1185 , H03M13/616 , H04L1/0043 , H04L1/0057
Abstract: A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 16200 and a code rate of 5/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).
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30.发明申请公开(公告)号：US20190074931A1
公开(公告)日：2019-03-07
申请号：US16182419
申请日：2018-11-06
Inventor： Sung-Ik PARK , Jae-Young LEE , Sun-Hyoung KWON , Heung-Mook KIM , Nam-Ho HUR
Abstract: An apparatus and method for multiplexing signals using layered division multiplexing are disclosed. A signal multiplexing apparatus according to an embodiment of the present invention includes a combiner configured to combine a core layer signal and an enhanced layer signal at different power levels to generate a multiplexed signal, a power normalizer configured to reduce power of the multiplexed signal to power corresponding to the core layer signal, and a time interleaver configured to perform interleaving applied to both the core layer signal and the enhanced layer signal.
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