公开(公告)号：US20140203827A1

公开(公告)日：2014-07-24

申请号：US13747579

申请日：2013-01-23

Applicant: GLOBALFOUNDRIES, INC.

Inventor： Sarasvathi Thangaraju ,  Chun Yu Wong

IPC: G01R27/14 ,  H01L23/48 ,  H01L21/768

CPC classification number: H01L21/76807 ,  H01L21/76898 ,  H01L23/528 ,  H01L23/5286 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Integrated circuits, methods of forming integrated circuits, and methods of sensing voiding between a through-semiconductor via and a subsequent layer that overlies the through-semiconductor via in integrated circuits are provided. An exemplary method of forming an integrated circuit includes forming a plurality of semiconductor devices on a semiconductor substrate. A through-semiconductor via is formed in the semiconductor substrate, and an interlayer dielectric layer is formed that overlies the through-semiconductor via and the plurality of semiconductor devices. A first interconnect via is embedded within the interlayer dielectric layer, and a second interconnect via is embedded within the interlayer dielectric layer. The first interconnect via and the second interconnect via are in electrical communication with the through-semiconductor via at spaced locations from each other on the through-semiconductor via.

Abstract translation: 提供集成电路，形成集成电路的方法以及在集成电路中覆盖贯穿半导体通孔的贯穿半导体通孔和后续层之间感应空隙的方法。 形成集成电路的示例性方法包括在半导体衬底上形成多个半导体器件。 在半导体衬底中形成贯通半导体通孔，并且形成覆盖贯通半导体通孔和多个半导体器件的层间电介质层。 第一互连通孔嵌入在层间电介质层内，并且第二互连通孔嵌入在层间电介质层内。 第一互连通孔和第二互连通孔在穿通半导体通孔上与穿通半导体通孔彼此间隔开的位置电连通。