公开(公告)号：US09245790B2

公开(公告)日：2016-01-26

申请号：US13747579

申请日：2013-01-23

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Sarasvathi Thangaraju ,  Chun Yu Wong

IPC: H01L29/40 ,  H01L21/768 ,  H01L23/528

CPC classification number: H01L21/76807 ,  H01L21/76898 ,  H01L23/528 ,  H01L23/5286 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Integrated circuits, methods of forming integrated circuits, and methods of sensing voiding between a through-semiconductor via and a subsequent layer that overlies the through-semiconductor via in integrated circuits are provided. An exemplary method of forming an integrated circuit includes forming a plurality of semiconductor devices on a semiconductor substrate. A through-semiconductor via is formed in the semiconductor substrate, and an interlayer dielectric layer is formed that overlies the through-semiconductor via and the plurality of semiconductor devices. A first interconnect via is embedded within the interlayer dielectric layer, and a second interconnect via is embedded within the interlayer dielectric layer. The first interconnect via and the second interconnect via are in electrical communication with the through-semiconductor via at spaced locations from each other on the through-semiconductor via.

Abstract translation: 提供集成电路，形成集成电路的方法以及在集成电路中覆盖贯穿半导体通孔的贯穿半导体通孔和后续层之间感应空隙的方法。 形成集成电路的示例性方法包括在半导体衬底上形成多个半导体器件。 在半导体衬底中形成贯通半导体通孔，并且形成覆盖贯通半导体通孔和多个半导体器件的层间电介质层。 第一互连通孔嵌入在层间电介质层内，并且第二互连通孔嵌入在层间电介质层内。 第一互连通孔和第二互连通孔在穿通半导体通孔上与穿通半导体通孔彼此间隔开的位置电连通。

公开(公告)号：US08895211B2

公开(公告)日：2014-11-25

申请号：US13710498

申请日：2012-12-11

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Guoxiang Ning ,  Chunyu Wong ,  Paul Ackmann ,  Sarasvathi Thangaraju

IPC: G03F1/26

CPC classification number: G03F7/20 ,  G03F1/28 ,  G03F1/42 ,  G03F1/50

Abstract: A mask is disclosed which includes a plurality of first phase shift regions disposed on a first side of the mask, and a plurality of second phase shift regions disposed on a second side of the mask. The first phase shift regions and second phase shift regions may be alternating phase shift regions in which phase shift of the first phase shift regions is out of phase, for instance by 180 degrees, from phase shift of the second phase shift regions. A method for forming the mask, and a semiconductor device fabrication method using the mask is also disclosed.

Abstract translation: 公开了一种掩模，其包括设置在掩模的第一侧上的多个第一相移区域和设置在掩模的第二侧上的多个第二相移区域。 第一相移区域和第二相移区域可以是交变相移区域，其中第一相移区域的相移与第二相移区域的相移相异，例如180度。 还公开了一种形成掩模的方法和使用该掩模的半导体器件制造方法。

公开(公告)号：US09761481B2

公开(公告)日：2017-09-12

申请号：US13748159

申请日：2013-01-23

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Chun Yu Wong ,  Sarasvathi Thangaraju ,  Percival Rayo

IPC: H01L21/768 ,  H01L23/528

CPC classification number: H01L21/76807 ,  H01L21/76898 ,  H01L23/528 ,  H01L23/5286 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Integrated circuits and methods of forming integrated circuits are provided herein, in which a plurality of semiconductor devices is formed on a semiconductor substrate. At least one through-semiconductor via is formed in the semiconductor substrate and an interlayer dielectric layer is formed overlying the at least one through-semiconductor via and the plurality of semiconductor devices. A first pattern is etched in the interlayer dielectric layer over the at least one through-semiconductor via, and a second pattern different from the first pattern is etched in the interlayer dielectric layer over the same through-semiconductor via as the first pattern. At least one interconnect via is embedded within the interlayer dielectric layer, in electrical communication with one of the at least one through-semiconductor vias. A metal-containing material is deposited in the first pattern and the second pattern to form a first metal layer in electrical communication with the at least one interconnect via.

公开(公告)号：US08907496B1

公开(公告)日：2014-12-09

申请号：US13909301

申请日：2013-06-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： GuoXiang Ning ,  Xiang Hu ,  Sarasvathi Thangaraju ,  Paul Ackmann

IPC: H01L21/768 ,  H01L23/522

CPC classification number: H01L23/5226 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Circuit structures and methods of fabrication are provided with enhanced electrical connection between, for instance, a first metal level and a contact surface of a conductive structure. Enhanced electrical connection is achieved using a plurality of contact vias which are differently-sized, and disposed over and electrically coupled to the contact surface. The differently-sized contact vias include at least one center region contact via disposed over a center region of the contact surface, and at least one peripheral region contact via disposed over a peripheral region of the contact surface, where the at least one center region contact via is larger than the at least one peripheral region contact via.

Abstract translation: 电路结构和制造方法在例如第一金属水平和导电结​​构的接触表面之间提供增强的电连接。 使用多个不同尺寸的接触通孔实现增强的电连接，并且设置在接触表面上并电耦合到接触表面。 不同尺寸的接触通孔包括设置在接触表面的中心区域上的至少一个中心区域接触孔，以及设置在接触表面的周边区域上的至少一个周边区域接触孔，其中该至少一个中心区域接触 通孔大于至少一个周边区域接触通孔。

公开(公告)号：US20160372425A1

公开(公告)日：2016-12-22

申请号：US15247513

申请日：2016-08-25

Applicant: GLOBALFOUNDRIES INC.

Inventor： Huang Liu ,  Sarasvathi Thangaraju ,  Chun Yu Wong

IPC: H01L23/00 ,  H01L21/48 ,  H01L25/07 ,  H01L23/498

CPC classification number: H01L23/562 ,  H01L21/486 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/49894 ,  H01L25/072 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Aspects of the present invention generally relate to approaches for forming a semiconductor device such as a TSV device having a “buffer zone” or gap layer between the TSV and transistor(s). The gap layer is typically filled with a low stress, thin film fill material that controls stresses and crack formation on the devices. Further, the gap layer ensures a certain spatial distance between TSVs and transistors to reduce the adverse effects of temperature excursion.

Abstract translation: 本发明的方面通常涉及用于形成半导体器件的方法，例如在TSV和晶体管之间具有“缓冲区”或间隙层的TSV器件。 间隙层通常填充有低应力的薄膜填充材料，其控制装置上的应力和裂纹形成。 此外，间隙层确保TSV和晶体管之间的一定空间距离，以减少温度偏移的不利影响。

公开(公告)号：US20140203827A1

公开(公告)日：2014-07-24

申请号：US13747579

申请日：2013-01-23

Applicant: GLOBALFOUNDRIES, INC.

Inventor： Sarasvathi Thangaraju ,  Chun Yu Wong

IPC: G01R27/14 ,  H01L23/48 ,  H01L21/768

CPC classification number: H01L21/76807 ,  H01L21/76898 ,  H01L23/528 ,  H01L23/5286 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Integrated circuits, methods of forming integrated circuits, and methods of sensing voiding between a through-semiconductor via and a subsequent layer that overlies the through-semiconductor via in integrated circuits are provided. An exemplary method of forming an integrated circuit includes forming a plurality of semiconductor devices on a semiconductor substrate. A through-semiconductor via is formed in the semiconductor substrate, and an interlayer dielectric layer is formed that overlies the through-semiconductor via and the plurality of semiconductor devices. A first interconnect via is embedded within the interlayer dielectric layer, and a second interconnect via is embedded within the interlayer dielectric layer. The first interconnect via and the second interconnect via are in electrical communication with the through-semiconductor via at spaced locations from each other on the through-semiconductor via.

Abstract translation: 提供集成电路，形成集成电路的方法以及在集成电路中覆盖贯穿半导体通孔的贯穿半导体通孔和后续层之间感应空隙的方法。 形成集成电路的示例性方法包括在半导体衬底上形成多个半导体器件。 在半导体衬底中形成贯通半导体通孔，并且形成覆盖贯通半导体通孔和多个半导体器件的层间电介质层。 第一互连通孔嵌入在层间电介质层内，并且第二互连通孔嵌入在层间电介质层内。 第一互连通孔和第二互连通孔在穿通半导体通孔上与穿通半导体通孔彼此间隔开的位置电连通。

公开(公告)号：US10043764B2

公开(公告)日：2018-08-07

申请号：US15247513

申请日：2016-08-25

Applicant: GLOBALFOUNDRIES INC.

Inventor： Huang Liu ,  Sarasvathi Thangaraju ,  Chun Yu Wong

IPC: H01L23/00 ,  H01L23/48 ,  H01L21/768 ,  H01L21/48 ,  H01L23/498 ,  H01L25/07

Abstract: Aspects of the present invention generally relate to approaches for forming a semiconductor device such as a TSV device having a “buffer zone” or gap layer between the TSV and transistor(s). The gap layer is typically filled with a low stress, thin film fill material that controls stresses and crack formation on the devices. Further, the gap layer ensures a certain spatial distance between TSVs and transistors to reduce the adverse effects of temperature excursion.

公开(公告)号：US09658531B2

公开(公告)日：2017-05-23

申请号：US14475967

申请日：2014-09-03

Applicant: GLOBALFOUNDRIES, INC.

Inventor： Guoxiang Ning ,  Chunyu Wong ,  Paul Ackmann ,  Sarasvathi Thangaraju

IPC: G03F1/26 ,  G03F7/20 ,  G03F1/28 ,  G03F1/50 ,  G03F1/42

CPC classification number: G03F7/20 ,  G03F1/28 ,  G03F1/42 ,  G03F1/50

Abstract: A mask is disclosed which includes a plurality of first phase shift regions disposed on a first side of the mask, and a plurality of second phase shift regions disposed on a second side of the mask. The first phase shift regions and second phase shift regions may be alternating phase shift regions in which phase shift of the first phase shift regions is out of phase, for instance by 180 degrees, from phase shift of the second phase shift regions. A method for forming the mask, and a semiconductor device fabrication method using the mask is also disclosed.

公开(公告)号：US09455188B2

公开(公告)日：2016-09-27

申请号：US13744551

申请日：2013-01-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Huang Liu ,  Sarasvathi Thangaraju ,  Chun Yu Wong

IPC: H01L23/48 ,  H01L21/336 ,  H01L21/768

CPC classification number: H01L23/562 ,  H01L21/486 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/49894 ,  H01L25/072 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Aspects of the present invention generally relate to approaches for forming a semiconductor device such as a TSV device having a “buffer zone” or gap layer between the TSV and transistor(s). The gap layer is typically filled with a low stress, thin film fill material that controls stresses and crack formation on the devices. Further, the gap layer ensures a certain spatial distance between TSVs and transistors to reduce the adverse effects of temperature excursion.

Abstract translation: 本发明的方面通常涉及用于形成半导体器件的方法，例如在TSV和晶体管之间具有“缓冲区”或间隙层的TSV器件。 间隙层通常填充有低应力的薄膜填充材料，其控制装置上的应力和裂纹形成。 此外，间隙层确保TSV和晶体管之间的一定空间距离，以减少温度偏移的不利影响。

公开(公告)号：US09236301B2

公开(公告)日：2016-01-12

申请号：US13939322

申请日：2013-07-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guoxiang Ning ,  Xiang Hu ,  Paul Ackmann ,  Sarasvathi Thangaraju

IPC: H01L21/44 ,  H01L21/768 ,  H01L23/48

CPC classification number: H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Fabrication of through-substrate via (TSV) structures is facilitated by: forming at least one stress buffer within a substrate; forming a through-substrate via contact within the substrate, wherein the through-substrate via structure and the stress buffer(s) are disposed adjacent to or in contact with each other; and where the stress buffer(s) includes a configuration or is disposed at a location relative to the through-substrate via conductor, at least in part, according to whether the TSV structure is an isolated TSV structure, a chained TSV structure, or an arrayed TSV structure, to customize stress alleviation by the stress buffer(s) about the through-substrate via conductor based, at least in part, on the type of TSV structure.

Abstract translation: 通过（TSV）结构制造贯穿衬底通过以下方式促进：在衬底内形成至少一个应力缓冲液; 通过所述衬底内的接触形成贯通衬底，其中所述贯通衬底通孔结构和所述应力缓冲器被设置为彼此相邻或接触; 并且其中所述应力缓冲器包括配置或者被布置在相对于所述贯通基板通孔导体的位置处，至少部分地根据所述TSV结构是否是隔离的TSV结构，链接的TSV结构或 至少部分地基于TSV结构的类型来定义通过基于导体的贯穿衬底的应力缓冲器的应力缓解。