JUNCTION OVERLAP CONTROL IN A SEMICONDUCTOR DEVICE USING A SACRIFICIAL SPACER LAYER
    21.
    发明申请
    JUNCTION OVERLAP CONTROL IN A SEMICONDUCTOR DEVICE USING A SACRIFICIAL SPACER LAYER 有权
    使用真空间隔层的半导体器件中的连接重叠控制

    公开(公告)号:US20150380514A1

    公开(公告)日:2015-12-31

    申请号:US14314404

    申请日:2014-06-25

    Abstract: Approaches for providing junction overlap control in a semiconductor device are provided. Specifically, at least one approach includes: providing a gate over a substrate; forming a set of junction extensions in a channel region adjacent the gate; forming a set of spacer layers along each of a set of sidewalls of the gate; removing the gate between the set of spacer layers to form an opening; removing, from within the opening, an exposed sacrificial spacer layer of the set of spacer layers, the exposed sacrificial spacer layer defining a junction extension overlap linear distance from the set of sidewalls of the gate; and forming a replacement gate electrode within the opening. This results in a highly scaled advanced transistor having precisely defined junction profiles and well-controlled gate overlap geometry achieved using extremely abrupt junctions whose surface position is defined using the set of spacer layers.

    Abstract translation: 提供了在半导体器件中提供接合重叠控制的方法。 具体地,至少一种方法包括:在衬底上提供栅极; 在与栅极相邻的沟道区域中形成一组结延伸部分; 沿着栅极的一组侧壁中的每一个形成一组间隔层; 移除所述一组间隔层之间的栅极以形成开口; 从所述开口内去除所述一组间隔层的暴露的牺牲间隔层,所述暴露的牺牲间隔层限定结延伸部与所述栅极侧壁的所述一组侧壁重叠线性距离; 以及在所述开口内形成替换栅电极。 这导致具有精确限定的接合轮廓的高度缩放的先进晶体管,并且使用极其突出的接头实现良好控制的栅极重叠几何,其表面位置使用该组间隔层限定。

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