公开(公告)号：US09769356B2

公开(公告)日：2017-09-19

申请号：US14694750

申请日：2015-04-23

Applicant: Google Inc.

Inventor： Ofer Shacham ,  Jason Rupert Redgrave ,  Albert Meixner ,  Qiuling Zhu ,  Daniel Frederic Finchelstein ,  David Patterson ,  Donald Stark

IPC: H04N3/14 ,  G06T1/60

CPC classification number: H04N3/1575 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30134 ,  G06T1/60

Abstract: An apparatus is described. The apparatus includes an execution lane array coupled to a two dimensional shift register array structure. Locations in the execution lane array are coupled to same locations in the two-dimensional shift register array structure such that different execution lanes have different dedicated registers.

公开(公告)号：US20170257585A1

公开(公告)日：2017-09-07

申请号：US15598027

申请日：2017-05-17

Applicant: Google Inc.

Inventor： Neeti Desai ,  Albert Meixner ,  Qiuling Zhu ,  Jason Rupert Redgrave ,  Ofer Shacham ,  Daniel Frederic Finchelstein

IPC: H04N5/369 ,  H04N5/91 ,  G06T1/60

CPC classification number: H04N5/3692 ,  G06T1/60 ,  H04N5/91

Abstract: An apparatus is described that include a line buffer unit composed of a plurality of a line buffer interface units. Each line buffer interface unit is to handle one or more requests by a respective producer to store a respective line group in a memory and handle one or more requests by a respective consumer to fetch and provide the respective line group from memory. The line buffer unit has programmable storage space whose information establishes line group size so that different line group sizes for different image sizes are storable in memory.

公开(公告)号：US20160316107A1

公开(公告)日：2016-10-27

申请号：US14694750

申请日：2015-04-23

Applicant: Google Inc.

Inventor： Ofer Shacham ,  Jason Rupert Redgrave ,  Albert Meixner ,  Qiuling Zhu ,  Daniel Frederic Finchelstein ,  David Patterson ,  Donald Stark

IPC: H04N3/14

CPC classification number: H04N3/1575 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30134 ,  G06T1/60

Abstract: An apparatus is described. The apparatus includes an execution lane array coupled to a two dimensional shift register array structure. Locations in the execution lane array are coupled to same locations in the two-dimensional shift register array structure such that different execution lanes have different dedicated registers.

Abstract translation: 描述了一种装置。 该装置包括耦合到二维移位寄存器阵列结构的执行通道阵列。 执行通道阵列中的位置耦合到二维移位寄存器阵列结构中的相同位置，使得不同的执行通道具有不同的专用寄存器。