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公开(公告)号：US20170257585A1
公开(公告)日：2017-09-07
申请号：US15598027
申请日：2017-05-17
Applicant: Google Inc.
Inventor： Neeti Desai , Albert Meixner , Qiuling Zhu , Jason Rupert Redgrave , Ofer Shacham , Daniel Frederic Finchelstein
CPC classification number: H04N5/3692 , G06T1/60 , H04N5/91
Abstract: An apparatus is described that include a line buffer unit composed of a plurality of a line buffer interface units. Each line buffer interface unit is to handle one or more requests by a respective producer to store a respective line group in a memory and handle one or more requests by a respective consumer to fetch and provide the respective line group from memory. The line buffer unit has programmable storage space whose information establishes line group size so that different line group sizes for different image sizes are storable in memory.
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Patent Agency Ranking
公开(公告)号：US20170256230A1
公开(公告)日：2017-09-07
申请号：US15599086
申请日：2017-05-18
Applicant: Google Inc.
Inventor： Albert Meixner , Neeti Desai , Dilan Manatunga , Jason Rupert Redgrave , William Mark
CPC classification number: G09G5/006 , G06F12/06 , G06T1/20 , G06T1/60 , G06T2200/28 , G09G5/02 , G09G2340/02 , H04N1/32358 , H04N2201/3291
Abstract: An image processor is described. The image processor includes an I/O unit to read input image data from external memory for processing by the image processor and to write output image data from the image processor into the external memory. The I/O unit includes multiple logical channel units. Each logical channel unit is to form a logical channel between the external memory and a respective producing or consuming component within the image processor. Each logical channel unit is designed to utilize reformatting circuitry and addressing circuitry. The addressing circuitry is to control addressing schemes applied to the external memory and reformatting of image data between external memory and the respective producing or consuming component. The reformatting circuitry is to perform the reformatting.
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3.发明申请ARCHITECTURE FOR HIGH PERFORMANCE, POWER EFFICIENT, PROGRAMMABLE IMAGE PROCESSING 有权高性能，高能效，可编程图像处理的架构公开(公告)号：US20160314555A1
公开(公告)日：2016-10-27
申请号：US14694828
申请日：2015-04-23
Applicant: Google Inc.
Inventor： Qiuling Zhu , Ofer Shacham , Albert Meixner , Jason Rupert Redgrave , Daniel Frederic Finchelstein , David Patterson , Neeti Desai , Donald Stark , Edward T. Chang , William R. Mark
Abstract: An apparatus is described. The apparatus includes an image processing unit. The image processing unit includes a network. The image processing unit includes a plurality of stencil processor circuits each comprising an array of execution unit lanes coupled to a two-dimensional shift register array structure to simultaneously process multiple overlapping stencils through execution of program code. The image processing unit includes a plurality of sheet generators respectively coupled between the plurality of stencil processors and the network. The sheet generators are to parse input line groups of image data into input sheets of image data for processing by the stencil processors, and, to form output line groups of image data from output sheets of image data received from the stencil processors. The image processing unit includes a plurality of line buffer units coupled to the network to pass line groups in a direction from producing stencil processors to consuming stencil processors to implement an overall program flow.
Abstract translation: 描述了一种装置。 该装置包括图像处理单元。 图像处理单元包括网络。 图像处理单元包括多个模板处理器电路，每个模板处理器电路各自包括耦合到二维移位寄存器阵列结构的执行单元通道的阵列，以通过执行程序代码来同时处理多个重叠模版。 图像处理单元包括分别耦合在多个模板处理器和网络之间的多个片材生成器。 片材生成器将图像数据的输入线组分解成图像数据的输入片以供模板处理器处理，并且从从模版处理器接收的图像数据的输出片材中形成图像数据的输出线组。 图像处理单元包括耦合到网络的多个行缓冲单元，以在从生成模板处理器到消耗模板处理器的方向上传递线组，以实现整个程序流程。
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公开(公告)号：US20170256021A1
公开(公告)日：2017-09-07
申请号：US15599348
申请日：2017-05-18
Applicant: Google Inc.
Inventor： Qiuling Zhu , Ofer Shacham , Albert Meixner , Jason Rupert Redgrave , Daniel Frederic Finchelstein , David Patterson , Neeti Desai , Donald Stark , Edward Chang , William Mark
Abstract: An apparatus is described. The apparatus includes an image processing unit. The image processing unit includes a plurality of stencil processor circuits each comprising an array of execution unit lanes coupled to a two-dimensional shift register array structure to simultaneously process multiple overlapping stencils through execution of program code. The image processing unit includes a plurality of sheet generators respectively coupled between the plurality of stencil processors and the network. The sheet generators are to parse input line groups of image data into input sheets of image data for processing by the stencil processors, and, to form output line groups of image data from output sheets of image data received from the stencil processors. The image processing unit includes a plurality of line buffer units coupled to the network to pass line groups in a direction from producing stencil processors to consuming stencil processors to implement an overall program flow.
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公开(公告)号：US20160316157A1
公开(公告)日：2016-10-27
申请号：US14694712
申请日：2015-04-23
Applicant: Google Inc.
Inventor： Neeti Desai , Albert Meixner , Qiuling Zhu , Jason Rupert Redgrave , Ofer Shacham , Daniel Frederic Finchelstein
CPC classification number: H04N5/3692 , G06T1/60 , H04N5/91
Abstract: An apparatus is described that include a line buffer unit composed of a plurality of a line buffer interface units. Each line buffer interface unit is to handle one or more requests by a respective producer to store a respective line group in a memory and handle one or more requests by a respective consumer to fetch and provide the respective line group from memory. The line buffer unit has programmable storage space whose information establishes line group size so that different line group sizes for different image sizes are storable in memory.
Abstract translation: 描述了包括由多个行缓冲器接口单元组成的行缓冲器单元的装置。 每个行缓冲器接口单元是处理相应制造商的一个或多个请求以将相应的行组存储在存储器中并且处理相应消费者的一个或多个请求以从存储器提取并提供相应的行组。 行缓冲单元具有可编程存储空间，其信息建立线组大小，使得用于不同图像大小的不同线组大小可存储在存储器中。
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公开(公告)号：US09756268B2
公开(公告)日：2017-09-05
申请号：US14694712
申请日：2015-04-23
Applicant: Google Inc.
Inventor： Neeti Desai , Albert Meixner , Qiuling Zhu , Jason Rupert Redgrave , Ofer Shacham , Daniel Frederic Finchelstein
CPC classification number: H04N5/3692 , G06T1/60 , H04N5/91
Abstract: An apparatus is described that include a line buffer unit composed of a plurality of a line buffer interface units. Each line buffer interface unit is to handle one or more requests by a respective producer to store a respective line group in a memory and handle one or more requests by a respective consumer to fetch and provide the respective line group from memory. The line buffer unit has programmable storage space whose information establishes line group size so that different line group sizes for different image sizes are storable in memory.
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