公开(公告)号：US20210004232A1

公开(公告)日：2021-01-07

申请号：US17001097

申请日：2020-08-24

Applicant: Google LLC

Inventor： Albert Meixner ,  Jason Rupert Redgrave ,  Ofer Shacham ,  Daniel Frederic Finchelstein ,  Qiuling Zhu

IPC: G06F9/38 ,  G06T1/20 ,  G06F9/30 ,  G06F15/80 ,  H04N3/14

Abstract: An apparatus that includes a program controller to fetch and issue instructions is described. The apparatus includes an execution lane having at least one execution unit to execute the instructions. The execution lane is part of an execution lane array that is coupled to a two dimensional shift register array structure, wherein, execution lane s of the execution lane array are located at respective array locations and are coupled to dedicated registers at same respective array locations in the two-dimensional shift register array.

公开(公告)号：US10791284B2

公开(公告)日：2020-09-29

申请号：US16659702

申请日：2019-10-22

Applicant: Google LLC

Inventor： Qiuling Zhu ,  Ofer Shacham ,  Jason Rupert Redgrave ,  Daniel Frederic Finchelstein ,  Albert Meixner

IPC: G09G5/36 ,  H04N5/262 ,  G06T1/60 ,  G06T1/20

Abstract: In a general aspect, an apparatus can include image processing logic (IPL) configured to perform an image processing operation on pixel data corresponding with an image having a width of W pixels and a height of H pixels to produce output pixel data in vertical slices of K pixels using K vertically overlapping stencils of S×S pixels, K being greater than 1 and less than H, S being greater than or equal to 2, and W being greater than S. The apparatus can also include a linebuffer operationally coupled with the IPL, the linebuffer configured to buffer the pixel data for the IPL. The linebuffer can include a full-size buffer having a width of W and a height of (S−1). The linebuffer can also include a sliding buffer having a width of SB and a height of K, SB being greater than or equal to S and less than W.

公开(公告)号：US10685423B2

公开(公告)日：2020-06-16

申请号：US16585834

申请日：2019-09-27

Applicant: Google LLC

Inventor： Hyunchul Park ,  Albert Meixner ,  Qiuling Zhu ,  William Mark

IPC: G06T1/60 ,  G06T1/20 ,  G09G5/36 ,  G06F3/06 ,  G06F9/50 ,  G06F30/20 ,  G06F30/33 ,  G06F12/084 ,  G06F12/0842 ,  G06F117/08

Abstract: A method is described. The method includes simulating execution of an image processing application software program. The simulating includes intercepting kernel-to-kernel communications with simulated line buffer memories that store and forward lines of image data communicated from models of producing kernels to models of consuming kernels. The simulating further includes tracking respective amounts of image data stored in the respective line buffer memories over a simulation runtime. The method also includes determining respective hardware memory allocations for corresponding hardware line buffer memories from the tracked respective amounts of image data. The method also includes generating configuration information for an image processor to execute the image processing application software program. The configuration information describes the hardware memory allocations for the hardware line buffer memories of the image processor.

公开(公告)号：US10430919B2

公开(公告)日：2019-10-01

申请号：US15594512

申请日：2017-05-12

Applicant: Google LLC

Inventor： Hyunchul Park ,  Albert Meixner ,  Qiuling Zhu ,  William Mark

IPC: G06F17/50 ,  G06T1/60 ,  G06T1/20 ,  G06F3/06 ,  G09G5/36 ,  G06F9/50 ,  G06F12/084 ,  G06F12/0842

Abstract: A method is described. The method includes simulating execution of an image processing application software program. The simulating includes intercepting kernel-to-kernel communications with simulated line buffer memories that store and forward lines of image data communicated from models of producing kernels to models of consuming kernels. The simulating further includes tracking respective amounts of image data stored in the respective line buffer memories over a simulation runtime. The method also includes determining respective hardware memory allocations for corresponding hardware line buffer memories from the tracked respective amounts of image data. The method also includes generating configuration information for an image processor to execute the image processing application software program. The configuration information describes the hardware memory allocations for the hardware line buffer memories of the image processor.

公开(公告)号：US20190238758A1

公开(公告)日：2019-08-01

申请号：US16376479

申请日：2019-04-05

Applicant: Google LLC

Inventor： Qiuling Zhu ,  Ofer Shacham ,  Jason Rupert Redgrave ,  Daniel Frederic Finchelstein ,  Albert Meixner

IPC: H04N5/262 ,  G06T1/20 ,  G06T1/60

Abstract: In a general aspect, an apparatus can include image processing logic (IPL) configured to perform an image processing operation on pixel data corresponding with an image having a width of W pixels and a height of H pixels to produce output pixel data in vertical slices of K pixels using K vertically overlapping stencils of S×S pixels, K being greater than 1 and less than H, S being greater than or equal to 2, and W being greater than S. The apparatus can also include a linebuffer operationally coupled with the IPL, the linebuffer configured to buffer the pixel data for the IPL. The linebuffer can include a full-size buffer having a width of W and a height of (S−1). The linebuffer can also include a sliding buffer having a width of SB and a height of K, SB being greater than or equal to S and less than W.

公开(公告)号：US10560598B2

公开(公告)日：2020-02-11

申请号：US16291047

申请日：2019-03-04

Applicant: Google LLC

Inventor： Albert Meixner ,  Jason Rupert Redgrave ,  Ofer Shacham ,  Qiuling Zhu ,  Daniel Frederic Finchelstein

IPC: H04N1/32 ,  G06T1/60 ,  B41F15/08

Abstract: A sheet generator circuit is described. The sheet generator includes electronic circuitry to receive a line group of image data including multiple rows of data from a frame of image data. The multiple rows are sufficient in number to encompass multiple neighboring overlapping stencils. The electronic circuitry is to parse the line group into a smaller sized sheet. The electronic circuitry is to load the sheet into a data computation unit having a two dimensional shift array structure coupled to an array of processors.

公开(公告)号：US10516833B2

公开(公告)日：2019-12-24

申请号：US16376479

申请日：2019-04-05

Applicant: Google LLC

Inventor： Qiuling Zhu ,  Ofer Shacham ,  Jason Rupert Redgrave ,  Daniel Frederic Finchelstein ,  Albert Meixner

IPC: G09G5/36 ,  H04N5/262 ,  G06T1/60 ,  G06T1/20

Abstract: In a general aspect, an apparatus can include image processing logic (IPL) configured to perform an image processing operation on pixel data corresponding with an image having a width of W pixels and a height of H pixels to produce output pixel data in vertical slices of K pixels using K vertically overlapping stencils of S×S pixels, K being greater than 1 and less than H, S being greater than or equal to 2, and W being greater than S. The apparatus can also include a linebuffer operationally coupled with the IPL, the linebuffer configured to buffer the pixel data for the IPL. The linebuffer can include a full-size buffer having a width of W and a height of (S−1). The linebuffer can also include a sliding buffer having a width of SB and a height of K, SB being greater than or equal to S and less than W.

公开(公告)号：US20190327433A1

公开(公告)日：2019-10-24

申请号：US16402310

申请日：2019-05-03

Applicant: Google LLC

Inventor： Neeti Desai ,  Albert Meixner ,  Qiuling Zhu ,  Jason Rupert Redgrave ,  Ofer Shacham ,  Daniel Frederic Finchelstein

IPC: H04N5/369 ,  H04N5/91 ,  G06T1/60

Abstract: An apparatus is described that include a line buffer unit composed of a plurality of a line buffer interface units. Each line buffer interface unit is to handle one or more requests by a respective producer to store a respective line group in a memory and handle one or more requests by a respective consumer to fetch and provide the respective line group from memory. The line buffer unit has programmable storage space whose information establishes line group size so that different line group sizes for different image sizes are storable in memory.

公开(公告)号：US10397450B2

公开(公告)日：2019-08-27

申请号：US15590849

申请日：2017-05-09

Applicant: Google LLC

Inventor： Ofer Shacham ,  Jason Rupert Redgrave ,  Albert Meixner ,  Qiuling Zhu ,  Daniel Frederic Finchelstein ,  David Patterson ,  Donald Stark

IPC: H04N3/14 ,  G06T1/60 ,  G06F9/30

Abstract: An apparatus is described. The apparatus includes an execution lane array coupled to a two dimensional shift register array structure. Locations in the execution lane array are coupled to same locations in the two-dimensional shift register array structure such that different execution lanes have different dedicated registers.

公开(公告)号：US20190208075A1

公开(公告)日：2019-07-04

申请号：US16291047

申请日：2019-03-04

Applicant: Google LLC

Inventor： Albert Meixner ,  Jason Rupert Redgrave ,  Ofer Shacham ,  Qiuling Zhu ,  Daniel Frederic Finchelstein

IPC: H04N1/32 ,  B41F15/08 ,  G06T1/60

Abstract: A sheet generator circuit is described. The sheet generator includes electronic circuitry to receive a line group of image data including multiple rows of data from a frame of image data. The multiple rows are sufficient in number to encompass multiple neighboring overlapping stencils. The electronic circuitry is to parse the line group into a smaller sized sheet. The electronic circuitry is to load the sheet into a data computation unit having a two dimensional shift array structure coupled to an array of processors.