公开(公告)号：US08930291B1

公开(公告)日：2015-01-06

申请号：US13708823

申请日：2012-12-07

Applicant: HRL Laboratories, LLC

Inventor： Narayan Srinivasa ,  Jose Cruz-Albrecht ,  Youngkwon Cho

IPC: G06N3/06 ,  G06N3/04 ,  G06N3/02

CPC classification number: G06N3/063 ,  G06N3/02 ,  G06N3/049 ,  G06N3/06

Abstract: A cortical neuromorphic network, system and method employ a plurality of neuromorphic nodes arranged in a network layer. The cortical neuromorphic network includes a neuromorphic node of the network layer in which the neuromorphic node includes a spike timing dependent plasticity (STDP) synapse and a neuromorphic neuron. The neuromorphic node is configured to receive a feedforward spike signal from selected ones of a plurality of input neurons of an input layer and to provide an output spike signal as a recurrent spike signal to the neuromorphic nodes of the network layer. A combination of the recurrent and feedforward spike signals is an excitatory spike signal of the neuromorphic node. The cortical neuromorphic system includes the neuromorphic nodes configured to operate according to a cycle and time slots of synaptic time multiplexing. The method includes receiving and weighting the excitatory spike signal using the STDP synapse and producing the output spike signal.

Abstract translation: 皮质神经元网络，系统和方法采用布置在网络层中的多个神经元节点。 皮质神经元网络包括网络层的神经元节点，其中神经元节点包括尖峰定时依赖性可塑性（STDP）突触和神经形态神经元。 神经元节点被配置为从输入层的多个输入神经元中的选定的一个接收前馈尖峰信号，并且向网络层的神经元节点提供作为反复尖峰信号的输出尖峰信号。 复发和前馈尖峰信号的组合是神经形态节点的兴奋性尖峰信号。 皮质神经元系统包括配置为根据突触时间复用的周期和时隙进行操作的神经元节点。 该方法包括使用STDP突触接收和加权兴奋性尖峰信号并产生输出尖峰信号。

公开(公告)号：US20220121911A9

公开(公告)日：2022-04-21

申请号：US16447210

申请日：2019-06-20

Applicant: HRL Laboratories, LLC

Inventor： Jose Cruz-Albrecht ,  Timothy Derosier ,  Narayan Srinivasa

IPC: G06N3/063 ,  G06N3/08 ,  G06N3/04

Abstract: A reconfigurable neural circuit includes an array of processing nodes. Each processing node includes a single physical neuron circuit having only one input and an output, a single physical synapse circuit having a presynaptic input, and a single physical output coupled to the input of the neuron circuit, a weight memory for storing N synaptic conductance value or weights having an output coupled to the single physical synapse circuit, a single physical spike timing dependent plasticity (STDP) circuit having an output coupled to the weight memory, a first input coupled to the output of the neuron circuit, and a second input coupled to the presynaptic input, and interconnect circuitry connected to the presynaptic input and connected to the output of the single physical neuron circuit. The synapse circuit and the STDP circuit are each time multiplexed circuits. The interconnect circuitry in each respective processing node is coupled to the interconnect circuitry in each other processing node.

公开(公告)号：US20190318232A1

公开(公告)日：2019-10-17

申请号：US16447210

申请日：2019-06-20

Applicant: HRL Laboratories, LLC

Inventor： Jose Cruz-Albrecht ,  Timothy Derosier ,  Narayan Srinivasa

IPC: G06N3/063 ,  G06N3/08 ,  G06N3/04

Abstract: A reconfigurable neural circuit includes an array of processing nodes. Each processing node includes a single physical neuron circuit having only one input and an output, a single physical synapse circuit having a presynaptic input, and a single physical output coupled to the input of the neuron circuit, a weight memory for storing N synaptic conductance value or weights having an output coupled to the single physical synapse circuit, a single physical spike timing dependent plasticity (STDP) circuit having an output coupled to the weight memory, a first input coupled to the output of the neuron circuit, and a second input coupled to the presynaptic input, and interconnect circuitry connected to the presynaptic input and connected to the output of the single physical neuron circuit. The synapse circuit and the STDP circuit are each time multiplexed circuits. The interconnect circuitry in each respective processing node is coupled to the interconnect circuitry in each other processing node.

公开(公告)号：US10121234B2

公开(公告)日：2018-11-06

申请号：US15481220

申请日：2017-04-06

Applicant: HRL Laboratories, LLC

Inventor： Yongqiang Cao ,  Narayan Srinivasa

IPC: G06K9/00 ,  G06T5/50

Abstract: Described is a system for ghost removal in video footage. During operation, the system generates a background subtraction map and an original bounding box that surrounds a detected foreground object through background subtraction. A detected foreground map is then generated. The detected foreground map includes at least two detected foreground (DF) bounding boxes of detected foregrounds obtained by a difference of two consecutive frames in video footage. Further, the original bounding box is then trimmed into a trimmed box, the trimmed box being a smallest box that contains the at least two DF bounding boxes. The trimmed box is designated as containing a real-world object, which can then be used for object tracking.

公开(公告)号：US20170316311A1

公开(公告)日：2017-11-02

申请号：US15079899

申请日：2016-03-24

Applicant: HRL Laboratories, LLC

Inventor： Praveen K. Pilly ,  Nigel D. Stepp ,  Narayan Srinivasa

IPC: G06N3/08 ,  G06N5/04

CPC classification number: G06N3/08 ,  G06K9/4628 ,  G06K9/6249 ,  G06K9/6272 ,  G06K9/64 ,  G06N3/0454 ,  G06N3/0481 ,  G06N5/04

Abstract: Described is a sparse inference module that can be incorporated into a deep learning system. For example, the deep learning system includes a plurality of hierarchical feature channel layers, each feature channel layer having a set of filters. A plurality of sparse inference modules can be included such that a sparse inference module resides electronically within each feature channel layer. Each sparse inference module is configured to receive data and match the data against a plurality of pattern templates to generate a degree of match value for each of the pattern templates, with the degree of match values being sparsified such that only those degree of match values that exceed a predetermined threshold, or a fixed number of the top degree of match values, are provided to subsequent feature channels in the plurality of hierarchical feature channels, while other, losing degree of match values are quenched to zero.

公开(公告)号：US20170316310A1

公开(公告)日：2017-11-02

申请号：US15075063

申请日：2016-03-18

Applicant: HRL Laboratories, LLC

Inventor： Youngkwan Cho ,  Narayan Srinivasa

IPC: G06N3/08

CPC classification number: G06N3/08 ,  G01S7/414 ,  G01S7/417 ,  G06K9/00543 ,  G06K9/00805 ,  G06K9/4623 ,  G06K9/66 ,  G06N3/0445 ,  G06N3/049 ,  G06N3/088

Abstract: Described is a system for decoding spiking reservoirs even when the spiking reservoir has continuous synaptic plasticity. The system uses a set of training patterns to train a neural network having a spiking reservoir comprised of spiking neurons. A test pattern duration d is estimated for a set of test patterns P, and each test pattern is presented to the spiking reservoir for a duration of d/P seconds. Output spikes from the spiking reservoir are generated via readout neurons. The output spikes are measured and the measurements are used to compute firing rate codes, each firing rate code corresponding to a test pattern in the set of test patterns P. The firing rate codes are used to decode performance of the neural network by computing a discriminability index (DI) to discriminate between test patterns in the set of test patterns P.

公开(公告)号：US09515789B2

公开(公告)日：2016-12-06

申请号：US13779408

申请日：2013-02-27

Applicant: HRL LABORATORIES, LLC.

Inventor： Deying Zhang ,  Narayan Srinivasa

IPC: G06E1/00 ,  G06E3/00 ,  G06F15/18 ,  G06G7/00 ,  G06N3/02 ,  H04L5/00 ,  H04L27/26 ,  G06N3/063 ,  G06N3/08 ,  G06N3/04

CPC classification number: H04L5/0023 ,  G06N3/02 ,  G06N3/0454 ,  G06N3/049 ,  G06N3/063 ,  G06N3/08 ,  H04L27/264

Abstract: A Multiple Input Multiple Output (MIMO) Orthogonal Frequency Division Multiplexing (OFDM) system for inter-device communication is described. Information data from each neuromorphic chip is coded and modulated, on the basis of destination, into different channels. The parallel signals in different channels are sent serially using TDM to a central router. After signal grouping by a central switching controller, each group of signals may be delivered to corresponding transmitter in the central router for transmission to a corresponding receiver in the neuromorphic chip using TDM.

Abstract translation: 描述了用于设备间通信的多输入多输出（MIMO）正交频分复用（OFDM）系统。 来自每个神经元芯片的信息数据在目的地的基础上被编码和调制成不同的信道。 不同信道中的并行信号使用TDM串行发送到中央路由器。 在通过中央交换控制器进行信号分组之后，可以将每组信号传送到中央路由器中的相应发射机，以使用TDM传输到神经元芯片中的相应接收机。

公开(公告)号：US09430736B2

公开(公告)日：2016-08-30

申请号：US14094589

申请日：2013-12-02

Applicant: HRL LABORATORIES, LLC

Inventor： Corey Thibeault ,  Kirill Minkovich ,  Narayan Srinivasa

IPC: G06N3/04

CPC classification number: G06N3/049 ,  G06N3/063

Abstract: A neural network portion comprising N pre-synaptic neurons capable each of firing an action potential, wherein the number N can be encoded in a word of n bits; the neural network portion being provided for, upon firing of a number F of pre-synaptic neurons in a predetermined period of time: if F.n N, generating a second type message, the message comprising N bits and being encoded in words of n bits, wherein each one of said N pre-synaptic neurons is represented by a unique bit, each bit having a first value if the pre-synaptic neuron represented by the bit fired in said predetermined period of time, and a second value otherwise.

Abstract translation: 一种神经网络部分，包括能够发射动作电位的N个突触前神经元，其中所述数目N可以以n位的字编码; 所述神经网络部分在预定时间段内触发数个F的突触前神经元时被提供;如果F n N，则生成第二类型消息，所述消息包括N位并以n位的字编码，其中所述N个突触前神经元中的每一个由唯一位表示，每个位具有第一值if 在所述预定时间段内由位触发表示的突触前神经元，否则为第二值。

公开(公告)号：US09412051B1

公开(公告)日：2016-08-09

申请号：US14296409

申请日：2014-06-04

Applicant: HRL Laboratories, LLC

Inventor： Suhas E. Chelian ,  Narayan Srinivasa

IPC: G06K9/00 ,  G06K9/66 ,  G06N3/04

CPC classification number: G06K9/4628 ,  G06N3/0445 ,  G06N3/049

Abstract: Neuromorphic image processing employs neuromorphic neurons arranged as relay neurons, interneurons and reticular neurons to process image data. A neuromorphic image processing channel includes relay neurons and interneurons to receive spiking input signals. The interneurons provide feed-forward inhibition to the relay neurons. The neuromorphic image processing channel also includes reticular neurons to receive output spiking signals from and to provide feedback inhibition to the relay neurons. A neuromorphic image processing system includes a first neuromorphic image processing (NIP) channel to receive a first set of spiking input signals and a second NIP channel to receive a second set of spiking input signals. The neuromorphic image processing system also includes reticular neurons to receive output spiking signals from and to provide feedback inhibition to both the first and second NIP channels.

Abstract translation: 神经形态图像处理采用神经元神经元作为中枢神经元，中间神经元和网状神经元来处理图像数据。 神经形态图像处理通道包括中继神经元和中间神经元以接收尖峰输入信号。 中间神经元向继电神经元提供前馈抑制。 神经形态图像处理通道还包括网状神经元以从中继神经元接收输出尖峰信号并向继电器神经元提供反馈抑制。 神经形态图像处理系统包括用于接收第一组尖峰输入信号的第一神经形态图像处理（NIP）信道和用于接收第二组尖峰输入信号的第二NIP信道。 神经形态图像处理系统还包括网状神经元以从第一和第二NIP通道向第二和第二NIP通道提供反馈抑制信号。

公开(公告)号：US09262843B1

公开(公告)日：2016-02-16

申请号：US14202200

申请日：2014-03-10

Applicant: HRL Laboratories, LLC

Inventor： Jose Cruz-Albrecht ,  Narayan Srinivasa

IPC: G06K9/46 ,  G06T9/00

CPC classification number: G06K9/4604 ,  G06K9/00986

Abstract: A circuit for detecting features in an image, the circuit including M time encoders, each time encoder having two inputs, Xi and Ti, where Xi is an ith element of an input vector X1 XM of the image and Ti is an ith element of a template vector T1 TM, and having an oscillatory output, wherein when the input vector X1 XM and the template vector T1 TM are more matched, the oscillatory outputs of the time encoders are more synchronized, and wherein when the input vector X1 XM and the template vector T1 TM are less matched, the oscillatory outputs of the time encoders are less synchronized.

Abstract translation: 一种用于检测图像中的特征的电路，包括M个时间编码器的电路，每次具有两个输入的编码器Xi和Ti，其中Xi是图像的输入矢量X1 XM的第i个元素，Ti是第i个元素 模板向量T1 TM，并且具有振荡输出，其中当输入矢量X1 XM和模板矢量T1 TM更匹配时，时间编码器的振荡输出更加同步，并且其中当输入矢量X1 XM和模板 矢量T1 TM较不匹配，时间编码器的振荡输出较少同步。