公开(公告)号：US5673743A

公开(公告)日：1997-10-07

申请号：US577472

申请日：1995-12-22

申请人： Hiroaki Kawamoto ,  Hidekazu Ito ,  Yuji Nishiyama ,  Masamitsu Kenmochi ,  Sadao Kitazawa ,  Makoto Iwata

发明人： Hiroaki Kawamoto ,  Hidekazu Ito ,  Yuji Nishiyama ,  Masamitsu Kenmochi ,  Sadao Kitazawa ,  Makoto Iwata

IPC分类号： B22C7/06 ,  B22C9/10 ,  B22C9/24 ,  B22C15/24

CPC分类号： B22C7/06 ,  B22C15/24 ,  B22C9/103

摘要： A process of core molding is disclosed, which permits increasing the positioning accuracy of a base core and a bonded core relative to each other and also avoids handling the first molded base core outside the die to preclude such trouble as breakage of the common die. By the process, a complete core is obtained, which comprises a base core and a bonded core positioned in and bonded to the base core. The base core is molded in a molding space which is defined by engaging a die element and a common die with each other. After removing the die element from the common die while leaving the molded base core in the common die, a different die element is engaged with the common die to define a different molding space for molding a bonded core. The bonded core is bonded to the base core as it is molded.

摘要翻译： 公开了一种芯成型的方法，其可以增加基底芯和接合芯相对于彼此的定位精度，并且还避免在模具外部处理第一模制基底芯以排除诸如共用裸片断裂的麻烦。 通过该过程，获得了一个完整的芯，其包括定位在基体芯中并与其结合的基底芯和粘结芯。 基底芯被模制在模制空间中，该模制空间通过将模具元件和公共模具彼此接合而限定。 在将模具基体芯离开共用模具之后，将模具元件从公共模具中取出之后，将不同的模具元件与公共模具接合以限定用于模制粘结芯的不同的模制空间。 粘合芯在成型时与基体芯结合。

公开(公告)号：US5457660A

公开(公告)日：1995-10-10

申请号：US131818

申请日：1993-10-05

申请人： Hidekazu Ito

发明人： Hidekazu Ito

IPC分类号： G06F1/24 ,  G06F12/16 ,  G11C7/00 ,  G06F7/38 ,  G06F19/00

CPC分类号： G06F1/24

摘要： In a reset signal generation circuit for generating a reset signal to a CPU in accordance with an external clock signal, illegal operation or loss of write data during a write period is prevented.A means (14) is provided for prohibiting the generation, in accordance with an external reset signal (RST), of a reset signal (RESET) to the CPU during a data write period of the CPU, and, according to a preferred embodiment of the invention, a means is provided for holding the external reset signal until a reset signal is generated to the CPU.

摘要翻译： 在用于根据外部时钟信号向CPU生成复位信号的复位信号生成电路中，防止写入期间的写入数据的非法操作或丢失。 提供了一种装置（14），用于在CPU的数据写入周期期间根据外部复位信号（＆amp; amp;＆amp; R）产生一个到CPU的复位信号（RESET），并且根据优选实施例 本发明提供一种用于保持外部复位信号的装置，直到向CPU产生复位信号为止。