公开(公告)号：US20060221034A1

公开(公告)日：2006-10-05

申请号：US11384363

申请日：2006-03-21

申请人： Takayuki Nakao ,  Hideo Sato ,  Masahiro Maki ,  Toshio Miyazawa

发明人： Takayuki Nakao ,  Hideo Sato ,  Masahiro Maki ,  Toshio Miyazawa

IPC分类号： G09G3/36

CPC分类号： G09G3/3655

摘要： The present invention provides a display device which includes a common electrode drive circuit having the single channel constitution which can miniaturize a circuit scale without increasing elements compared to a conventional display device. A display device includes a plurality of pixels and a common electrode drive circuit. The common electrode drive circuit includes a plurality of basic circuits, wherein the basic circuit includes a first circuit which latches a first input signal at a point of time that a clock signal is changed to a first voltage level from a second voltage level; a second circuit which latches a second input signal at the point of time that the clock signal is changed to the first voltage level from the second voltage level; a first switching circuit which is turned on based on the voltage latched by the first circuit and outputs a first power source voltage to an output terminal in an ON state; and a second switching circuit which is turned on based on the voltage which is latched by the second circuit and outputs a second power source voltage to an output terminal in an ON state, wherein when the first input signal assumes the second voltage level, the second input signal assumes the first voltage level, and when the second input signal assumes the second voltage level, the first input signal assumes the first voltage level, and after the clock signal is changed to the second voltage level from the first voltage level and before the clock signal returns to the first voltage level from the second voltage level, either one of the first input signal and the second input signal is changed to the second voltage level form the first voltage level.

摘要翻译： 本发明提供了一种显示装置，其包括具有单通道结构的公共电极驱动电路，其可以与常规显示装置相比能够使电路规模小型化而不增加元件。 显示装置包括多个像素和公共电极驱动电路。 公共电极驱动电路包括多个基本电路，其中基本电路包括第一电路，其在时钟信号从第二电压电平变为第一电压电平的时间点锁存第一输入信号; 第二电路，其在时钟信号从第二电压电平改变为第一电压电平的时间点锁存第二输入信号; 第一开关电路基于由第一电路锁存的电压而导通，并将第一电源电压输出到处于导通状态的输出端子; 以及第二开关电路，其基于由所述第二电路锁存的电压而导通，并将第二电源电压输出到处于导通状态的输出端子，其中当所述第一输入信号呈现所述第二电压电平时，所述第二开关电路 输入信号呈现第一电压电平，并且当第二输入信号呈现第二电压电平时，第一输入信号呈现第一电压电平，并且在时钟信号从第一电压电平变化到第二电压电平之后并且在 时钟信号从第二电压电平返回到第一电压电平，第一输入信号和第二输入信号中的任一个被改变为形成第一电压电平的第二电压电平。

公开(公告)号：US08217885B2

公开(公告)日：2012-07-10

申请号：US12379521

申请日：2009-02-24

申请人： Toshio Miyazawa ,  Masahiro Maki ,  Hideo Sato ,  Takumi Shigaki

发明人： Toshio Miyazawa ,  Masahiro Maki ,  Hideo Sato ,  Takumi Shigaki

IPC分类号： G09G3/36 ,  G11C19/00

CPC分类号： G09G3/3677 ,  G09G3/3688 ,  G09G2310/0286 ,  G11C19/184

摘要： In a display device which includes a driver circuit having a shift register circuit, the shift register circuit is constituted of basic circuits in plural stages. Each basic circuit is constituted of a circuit A, a circuit B and a circuit C. The circuit A fetches a first drive clock (or a second drive clock) inputted from the outside when transfer data is inputted to the circuit A from a circuit of preceding stage, outputs the transfer data as a shift output of own stage, and transfers the transfer data to the circuit B. The circuit B transfers the transfer data to the circuit A of the basic circuit of the succeeding stage, and resets the circuit C. The circuit C resets the circuit A and the circuit B in synchronism with the first drive clock (or the second drive clock) generated at next timing or succeeding timing of the first drive clock.

摘要翻译： 在包括具有移位寄存器电路的驱动电路的显示装置中，移位寄存器电路由多级的基本电路构成。 每个基本电路由电路A，电路B和电路C构成。当传输数据从电路A的电路输入到电路A时，电路A取出从外部输入的第一驱动时钟（或第二驱动时钟） 输出传输数据作为自身级的移位输出，并将传送数据传送到电路B.电路B将传送数据传送到后级基本电路的电路A，并将电路C 电路C与在第一驱动时钟的下一定时或后续定时产生的第一驱动时钟（或第二驱动时钟）同步地复位电路A和电路B.

公开(公告)号：US08164560B2

公开(公告)日：2012-04-24

申请号：US12729530

申请日：2010-03-23

申请人： Takayuki Nakao ,  Hideo Sato ,  Masahiro Maki ,  Toshio Miyazawa

发明人： Takayuki Nakao ,  Hideo Sato ,  Masahiro Maki ,  Toshio Miyazawa

IPC分类号： G09G3/36

CPC分类号： G09G3/3655

摘要： A display device is provided which includes a common electrode drive circuit having the single channel constitution which can miniaturize a circuit scale without increasing elements compared to a conventional display device. A display device includes a plurality of pixels and a common electrode drive circuit. The common electrode drive circuit includes a plurality of basic circuits, wherein the basic circuit includes a first circuit which latches a first input signal at a point of time that a clock signal is changed to a first voltage level from a second voltage level; a second circuit which latches a second input signal at the point of time that the clock signal is changed to the first voltage level from the second voltage level; a first switching circuit which is turned on based on the first circuit and a second switching circuit which is turned on based on the second circuit.

摘要翻译： 提供一种显示装置，其包括具有单通道结构的公共电极驱动电路，其可以与传统的显示装置相比能够使电路规模小型化而不增加元件。 显示装置包括多个像素和公共电极驱动电路。 公共电极驱动电路包括多个基本电路，其中基本电路包括第一电路，其在时钟信号从第二电压电平变为第一电压电平的时间点锁存第一输入信号; 第二电路，其在时钟信号从第二电压电平改变为第一电压电平的时间点锁存第二输入信号; 基于第一电路接通的第一开关电路和基于第二电路导通的第二开关电路。

公开(公告)号：US07724231B2

公开(公告)日：2010-05-25

申请号：US11384363

申请日：2006-03-21

申请人： Takayuki Nakao ,  Hideo Sato ,  Masahiro Maki ,  Toshio Miyazawa

发明人： Takayuki Nakao ,  Hideo Sato ,  Masahiro Maki ,  Toshio Miyazawa

IPC分类号： G09G3/36

CPC分类号： G09G3/3655

摘要： The present invention provides a display device which includes a common electrode drive circuit having the single channel constitution which can miniaturize a circuit scale without increasing elements compared to a conventional display device. A display device includes a plurality of pixels and a common electrode drive circuit. The common electrode drive circuit includes a plurality of basic circuits, wherein the basic circuit includes a first circuit which latches a first input signal at a point of time that a clock signal is changed to a first voltage level from a second voltage level; a second circuit which latches a second input signal at the point of time that the clock signal is changed to the first voltage level from the second voltage level; a first switching circuit which is turned on based on the first circuit; and a second switching circuit which is turned on based on the the second circuit.

摘要翻译： 本发明提供了一种显示装置，其包括具有单通道结构的公共电极驱动电路，其可以与常规显示装置相比能够使电路规模小型化而不增加元件。 显示装置包括多个像素和公共电极驱动电路。 公共电极驱动电路包括多个基本电路，其中基本电路包括第一电路，其在时钟信号从第二电压电平变为第一电压电平的时间点锁存第一输入信号; 第二电路，其在时钟信号从第二电压电平改变为第一电压电平的时间点锁存第二输入信号; 基于第一电路接通的第一开关电路; 以及基于第二电路接通的第二开关电路。

公开(公告)号：US20070194973A1

公开(公告)日：2007-08-23

申请号：US11702121

申请日：2007-02-05

申请人： Takayuki Nakao ,  Hideo Sato ,  Masahiro Maki ,  Toshio Miyazawa

发明人： Takayuki Nakao ,  Hideo Sato ,  Masahiro Maki ,  Toshio Miyazawa

IPC分类号： H03M1/12

CPC分类号： G09G3/3688 ,  G09G3/3208 ,  G09G3/3677 ,  G09G2300/0408 ,  G09G2310/0289 ,  G09G2330/021 ,  G11C19/184 ,  G11C19/28

摘要： The present invention provides a display device which includes a drive circuit having a CMOS shift register circuit constituted of a simple CMOS circuit. A drive circuit includes a shift register circuit, and the shift register circuit includes n(n≧2) pieces of basic circuits which are connected vertically in multiple stages. The basic circuit includes a first transistor of a first conductive type having a first electrode to which a clock is applied, a second transistor of a second conductive type different from the first conductive type in a conductive type and having a first electrode to which a second power source voltage is applied, and a third transistor of a first conductive type having a second electrode which is connected to the second electrode of the second transistor and a first electrode to which a first power source voltage different from the second power source voltage is applied, wherein the second electrode of the first transistor is connected to a control electrode of the third transistor, an input signal is applied to a control electrode of the first transistor and a control electrode of the second transistor, and a voltage of the second electrode of the third transistor forms a scanning circuit output.

摘要翻译： 本发明提供了一种显示装置，其包括具有由简单CMOS电路构成的CMOS移位寄存器电路的驱动电路。 驱动电路包括移位寄存器电路，并且移位寄存器电路包括多个垂直连接的n（n> = 2）个基本电路。 基本电路包括具有第一电极的第一导电类型的第一晶体管，施加时钟的第一电极，与导电类型不同于第一导电类型的第二导电类型的第二晶体管，并具有第一电极， 施加电源电压，并且具有连接到第二晶体管的第二电极的第二电极的第一导电类型的第三晶体管和施加不同于第二电源电压的第一电源电压的第一电极 其中第一晶体管的第二电极连接到第三晶体管的控制电极，输入信号施加到第一晶体管的控制电极和第二晶体管的控制电极，第二电极的电压 第三晶体管形成扫描电路输出。

公开(公告)号：US20070188672A1

公开(公告)日：2007-08-16

申请号：US11703161

申请日：2007-02-07

申请人： Hideo Sato ,  Shigeyuki Nishitani ,  Takayuki Nakao ,  Masahiro Maki

发明人： Hideo Sato ,  Shigeyuki Nishitani ,  Takayuki Nakao ,  Masahiro Maki

IPC分类号： G02F1/1333

CPC分类号： G09G3/3688 ,  G09G3/3677 ,  G09G2310/0289

摘要： A shift register circuit having a level conversion function is provided with a simple circuit configuration. Each basic circuit of the shift register circuit includes: a first transistor of a second conductivity type having a first electrode to which a second supply voltage is applied; a second transistor of the second conductivity type having a first electrode connected to a second electrode of the first transistor and a second electrode connected to an output node; a third transistor of a first conductivity type having a first electrode to which a first supply voltage is applied and a second electrode connected to the output node directly or through another transistor, the first conductivity type being different from the second conductivity type; and a fourth transistor of the first conductivity type having a first electrode to which the first supply voltage is applied and a second electrode connected to the second electrode of the third transistor, wherein a clock signal is supplied to a control electrode of the first transistor, a set signal is supplied to a control electrode of the second transistor, a clear signal is supplied to a control electrode of the third transistor, a reset signal is supplied to a control electrode of the fourth transistor, and a voltage of the output node is an output of a scanning circuit.

摘要翻译： 具有电平转换功能的移位寄存器电路具有简单的电路配置。 移位寄存器电路的每个基本电路包括：具有施加第二电源电压的第一电极的第二导电类型的第一晶体管; 第二导电类型的第二晶体管具有连接到第一晶体管的第二电极的第一电极和连接到输出节点的第二电极; 第一导电类型的第三晶体管具有施加第一电源电压的第一电极和直接或通过另一晶体管连接到输出节点的第二电极，第一导电类型不同于第二导电类型; 以及第一导电类型的第四晶体管，具有施加第一电源电压的第一电极和连接到第三晶体管的第二电极的第二电极，其中时钟信号被提供给第一晶体管的控制电极， 向第二晶体管的控制电极提供置位信号，向第三晶体管的控制电极提供清除信号，将复位信号提供给第四晶体管的控制电极，输出节点的电压为 扫描电路的输出。

公开(公告)号：US20050116654A1

公开(公告)日：2005-06-02

申请号：US10998002

申请日：2004-11-29

申请人： Hideo Sato ,  Tomohiko Sato ,  Masahiro Maki ,  Takayuki Nakao

发明人： Hideo Sato ,  Tomohiko Sato ,  Masahiro Maki ,  Takayuki Nakao

IPC分类号： G02F1/133 ,  G09G3/10 ,  G09G3/20 ,  G09G3/36 ,  H04N5/66

CPC分类号： G09G3/3688 ,  G09G3/3614 ,  G09G2310/0259 ,  G09G2310/027

摘要： Gamma correction of a video signal voltage applied to respective pixels of a display device can be accomplished without modulating a ramp voltage. The display device includes a common voltage generating circuit which selectively outputs a high-potential-side common voltage or a low-potential-side common voltage to common electrodes in response to an alternating signal, a data storage circuit, a reference data generating circuit which a ramp voltage generating circuit, a plurality of comparing circuits which compare data stored in the data storage circuit and the reference data generated by the reference data generating circuit, and a plurality of sampling circuits which sample the ramp voltage generated by the ramp voltage generating circuit in response to comparison results of the comparing circuits and output the sampled ramp voltage as a video signal voltage to respective video lines. The reference data generated by the reference data generating circuit is changed non-linearly with respect to time.

摘要翻译： 可以在不调制斜坡电压的情况下实现施加到显示装置的各个像素的视频信号电压的伽马校正。 显示装置包括：公共电压发生电路，其响应于交变信号选择性地向公共电极输出高电位侧公共电压或低电位侧公共电压;数据存储电路，参考数据生成电路， 斜坡电压产生电路，将数据存储电路中存储的数据与由基准数据产生电路产生的参考数据进行比较的多个比较电路，以及对由斜坡电压产生电路产生的斜坡电压进行采样的多个采样电路 响应于比较电路的比较结果，并将采样的斜坡电压作为视频信号电压输出到各个视频线。 由参考数据产生电路产生的参考数据相对于时间非线性地改变。

公开(公告)号：US08558779B2

公开(公告)日：2013-10-15

申请号：US13556283

申请日：2012-07-24

申请人： Hideo Sato ,  Shigeyuki Nishitani ,  Takayuki Nakao ,  Masahiro Maki

发明人： Hideo Sato ,  Shigeyuki Nishitani ,  Takayuki Nakao ,  Masahiro Maki

IPC分类号： G09G3/36 ,  G11C19/00

CPC分类号： G09G3/3688 ,  G09G3/3677 ,  G09G2310/0289

摘要： A display device comprises a driver circuit having a shift register circuit having a level conversion function is provided with a simple circuit configuration of first, second, and third basic circuits connected in tandem at multistages. A common clear signal is supplied to a control electrode of a third transistor of each basic circuit, a first clock is supplied to a control electrode of a first transistor of each of the first and third basic circuits, a second clock different in phase from the first clock is supplied to a control electrode of a first transistor of the second basic circuit, outputs of the first and second basic circuit are respectively supplied to control electrodes of second transistors of the second and third basic circuits, and an inversion output of the third basic circuit is supplied to a control electrode of a fourth transistor of the first basic circuit.

摘要翻译： 显示装置包括具有电平转换功能的移位寄存器电路的驱动电路具有以多级串联连接的第一，第二和第三基本电路的简单电路配置。 向每个基本电路的第三晶体管的控制电极提供公共的清除信号，第一时钟被提供给第一和第三基本电路中的每一个的第一晶体管的控制电极，与第 第一时钟被提供给第二基本电路的第一晶体管的控制电极，第一和第二基本电路的输出分别提供给第二和第三基本电路的第二晶体管的控制电极，第三基极的第二晶体管的反相输出 基本电路被提供给第一基本电路的第四晶体管的控制电极。

公开(公告)号：US08508513B2

公开(公告)日：2013-08-13

申请号：US12398326

申请日：2009-03-05

申请人： Takumi Shigaki ,  Toshio Miyazawa ,  Hideo Sato ,  Masahiro Maki

发明人： Takumi Shigaki ,  Toshio Miyazawa ,  Hideo Sato ,  Masahiro Maki

IPC分类号： G09G5/00

CPC分类号： G09G3/3648 ,  G09G3/3614 ,  G09G3/3655 ,  G09G3/3677 ,  G09G2310/0286 ,  G09G2310/06 ,  G11C19/28 ,  G11C19/287

摘要： A display device which enhances time-wise likelihood for a leak current from a floating memory node by increasing the number of writings of a voltage to a floating memory node. A vertical driver includes: a shift register including basic circuits which output common electrode driving pulses based on a transfer; and a common electrode driver including common basic circuits which receive the common electrode driving pulses and the transfer clock. Each common basic circuit includes: a circuit A which fetches an AC signal based on the common electrode driving pulse; a circuit B which outputs, based on the AC signal, a first common voltage or a second common voltage which differs from the first common voltage in voltage level to the common electrodes corresponding to the AC signal; and a circuit C which holds a state of the circuit B based on the transfer clock.

摘要翻译： 一种显示装置，其通过将电压写入数量增加到浮动存储器节点来增强来自浮动存储器节点的泄漏电流的时间似然。 垂直驱动器包括：移位寄存器，包括基于转移输出公共电极驱动脉冲的基本电路; 以及公共电极驱动器，其包括接收公共电极驱动脉冲和传送时钟的公共基本电路。 每个公共基本电路包括：基于公共电极驱动脉冲取出AC信号的电路A; 电路B，其基于所述AC信号，将与所述AC信号对应的公共电极的电压电平的第一公共电压不同的第一公共电压或第二公共电压输出; 以及基于传送时钟保持电路B的状态的电路C.

公开(公告)号：US08259055B2

公开(公告)日：2012-09-04

申请号：US11703161

申请日：2007-02-07

申请人： Hideo Sato ,  Shigeyuki Nishitani ,  Takayuki Nakao ,  Masahiro Maki

发明人： Hideo Sato ,  Shigeyuki Nishitani ,  Takayuki Nakao ,  Masahiro Maki

IPC分类号： G09G3/36 ,  G11C19/00

CPC分类号： G09G3/3688 ,  G09G3/3677 ,  G09G2310/0289

摘要： A display device comprises a driver circuit having a shift register circuit having a level conversion function is provided with a simple circuit configuration of first, second, and third basic circuits connected in tandem at multistages. A common clear signal is supplied to a control electrode or a third transistor of each basic circuit, a first clock is supplied to a control electrode of a first transistor of each of the first and third basic circuits, a second cock different in phase from the first clock is supplied to a control electrode of a first transistor of the second basic circuit, outputs of the first and second basic circuit are respectively supplied to control electrodes of second transistors of the second and third basic circuits, and an inversion output of the third basic circuit is supplied to a control electrode of a fourth transistor of the first basic circuit.

摘要翻译： 显示装置包括具有电平转换功能的移位寄存器电路的驱动电路具有以多级串联连接的第一，第二和第三基本电路的简单电路配置。 向每个基本电路的控制电极或第三晶体管提供公共的清除信号，第一时钟被提供给第一和第三基本电路中的每一个的第一晶体管的控制电极， 第一时钟被提供给第二基本电路的第一晶体管的控制电极，第一和第二基本电路的输出分别提供给第二和第三基本电路的第二晶体管的控制电极，第三基极的第二晶体管的反相输出 基本电路被提供给第一基本电路的第四晶体管的控制电极。