公开(公告)号：US11194381B2

公开(公告)日：2021-12-07

申请号：US16642203

申请日：2017-09-29

Applicant: INTEL CORPORATION

Inventor： Abhinav Karhu ,  Russell Fenger ,  Vijay Dhanraj ,  Balaji Masanamuthu Chinnathurai

IPC: G06F1/3234 ,  G06F1/3228 ,  G06F11/30

Abstract: Techniques and apparatus for managing performance states of processing circuitry of a computing device are described. In one embodiment, for example, an apparatus may include at least one memory, at least one processing circuitry, and logic, at least a portion of comprised in hardware coupled to the at least one processing circuitry, to set a first performance state (P-state) of the at least one processing circuitry based on system utilization information, access a performance interface element comprising a plurality of performance metric hints, update the first P-state to a second P-state responsive to one of the plurality of performance metric hints being set by an operating system (OS) of the apparatus, and maintain the first P-state responsive to none of the plurality of performance metric hints being set by the operating system (OS). Other embodiments are described and claimed.