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    Apparatuses, methods, and systems for instructions for a hardware assisted heterogeneous instruction set architecture dispatcher
    1.
    发明授权
    Apparatuses, methods, and systems for instructions for a hardware assisted heterogeneous instruction set architecture dispatcher 有权

    公开(公告)号：US12175247B2

    公开(公告)日：2024-12-24

    申请号：US17359306

    申请日：2021-06-25

    Applicant: Intel Corporation

    Inventor： Balaji Masanamuthu Chinnathurai ,  Kunal Mehta ,  Brian L. Vajda

    IPC: G06F9/30

    Abstract: Systems, methods, and apparatuses to support instructions for a hardware assisted heterogeneous instruction set architecture dispatcher are described. In one embodiment, a hardware processor includes a plurality of processor cores comprising a first type of processor core that supports a first instruction set architecture and a second type of processor core that supports a second different instruction set architecture, a decoder circuit of a processor core of the plurality of processor cores to decode a single instruction into a decoded single instruction, the single instruction including a field that identifies a requested core type and an opcode that indicates an execution circuit of the processor core is to: read a register to determine a core type of the processor core, cause the processor core to enter a first mode, that only permits execution of the first instruction set architecture by the processor core, when the requested core type and the core type of the processor core are the first type, cause the processor core to enter a second mode, that only permits execution of the second different instruction set architecture by the processor core, when the requested core type and the core type of the processor core are the second type, cause the processor core to enter a third mode, that only permits execution of the first instruction set architecture by the processor core, when the requested core type is the second type and the core type of the processor core is the first type, and cause the processor core to enter a fourth mode, that only permits execution of the second different instruction set architecture by the processor core, when the requested core type is the first type and the core type of the processor core is the second type, and the execution circuit of the processor core to execute the decoded single instruction according to the opcode.

    Techniques for controlling processor performance states
    4.
    发明授权
    Techniques for controlling processor performance states 有权

    公开(公告)号：US11194381B2

    公开(公告)日：2021-12-07

    申请号：US16642203

    申请日：2017-09-29

    Applicant: INTEL CORPORATION

    Inventor： Abhinav Karhu ,  Russell Fenger ,  Vijay Dhanraj ,  Balaji Masanamuthu Chinnathurai

    IPC: G06F1/3234 ,  G06F1/3228 ,  G06F11/30

    Abstract: Techniques and apparatus for managing performance states of processing circuitry of a computing device are described. In one embodiment, for example, an apparatus may include at least one memory, at least one processing circuitry, and logic, at least a portion of comprised in hardware coupled to the at least one processing circuitry, to set a first performance state (P-state) of the at least one processing circuitry based on system utilization information, access a performance interface element comprising a plurality of performance metric hints, update the first P-state to a second P-state responsive to one of the plurality of performance metric hints being set by an operating system (OS) of the apparatus, and maintain the first P-state responsive to none of the plurality of performance metric hints being set by the operating system (OS). Other embodiments are described and claimed.

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