公开(公告)号：US09596108B2

公开(公告)日：2017-03-14

申请号：US14292743

申请日：2014-05-30

Applicant: INTEL CORPORATION

Inventor： Sitaraman V. Iyer ,  Fulvio Spagna

IPC: H04L25/03 ,  H04L7/00

CPC classification number: H04L25/03949 ,  H04L7/0062 ,  H04L25/03146

Abstract: Described is an apparatus which comprises: a Decision Feedback Equalizer (DFE); and a phase detector, operationally coupled to the DFE, to set a sampling phase based on a first post-cursor value of a composite pulse response being substantially equal to zero when the phase detector collects data bits having current bit and next bit such that value of the current bit is unequal to a value of the next bit.

Abstract translation: 描述了一种装置，其包括：判决反馈均衡器（DFE）; 以及相位检测器，可操作地耦合到DFE，当相位检测器收集具有当前位和下一位的数据位时，基于复合脉冲响应的第一后标值来设置采样相位，该第一后置光标值基本上等于零， 的当前位不等于下一位的值。