公开(公告)号：US20190004920A1

公开(公告)日：2019-01-03

申请号：US15638727

申请日：2017-06-30

Applicant: Intel Corporation

Inventor： Yves Vandriessche ,  Wim Heirman ,  Ibrahim Hur ,  Kristof du Bois ,  Stijn Eyerman

IPC: G06F11/34 ,  G06F17/50 ,  G06N99/00

Abstract: Technologies for processor architecture simulation with machine learning include a computing device that simulates performance of a processor executing training programs with a simulation model. The computing device captures ground truth performance statistics of the processor executing the training programs, for example using a cycle-accurate simulator. The computing device collects training simulation statistics from the simulation model and trains an error model with the training simulation statistics as feature vector and with the ground truth performance statistics. The computing device may simulate performance of the processor executing a test program, capture test simulation statistic from the simulation model, and predict a predicted error of the simulation model using the error model with the test simulation statistics as feature vector. The computing device may adjust output of the simulation model or adapt execution of the simulation model based on the predicted error. Other embodiments are described and claimed.