公开(公告)号：US09207750B2

公开(公告)日：2015-12-08

申请号：US13715624

申请日：2012-12-14

Applicant: Intel Corporation

Inventor： Gururaj K. Shamanna ,  Stefan Rusu ,  Phani Kumar Kandula ,  Sankalan Prasad ,  Mandar R. Ranade ,  Narayanan Natarajan ,  Tessil Thomas

IPC: G06F1/32

CPC classification number: G06F1/28 ,  G05F1/625 ,  G06F1/3275 ,  G06F1/3296 ,  Y02D10/14 ,  Y02D10/172

Abstract: Described is a processor comprising: a plurality of transistors operable to provide dynamically adjustable transistor size, the plurality of transistors coupled at one end to a first power supply and coupled at another end to a second power supply; a circuit coupled to the second power supply, the second power supply to provide power to the circuit; and a power control unit (PCU) to monitor the level of the first power supply, and to dynamically adjust the transistor size of the plurality of transistors so that the second power supply is adjusted to keep the circuit operational.

Abstract translation: 描述了一种处理器，包括：多个晶体管，其可操作以提供动态可调节的晶体管尺寸，所述多个晶体管的一端耦合到第一电源并在另一端耦合到第二电源; 耦合到所述第二电源的电路，所述第二电源向所述电路提供电力; 以及功率控制单元（PCU），用于监测第一电源的电平，并且动态地调整多个晶体管的晶体管尺寸，使得调节第二电源以保持电路的可操作性。