公开(公告)号：US20220366968A1

公开(公告)日：2022-11-17

申请号：US17816442

申请日：2022-08-01

Applicant: Intel Corporation

Inventor： Renzhi Liu ,  Hechen Wang ,  Richard Dorrance ,  Deepak Dasalukunte

IPC: G11C11/4096 ,  G11C11/4094 ,  G11C11/408 ,  G06F7/544

Abstract: Technology for generating an SRAM-based in-memory computing macro includes replacing a SRAM cell cluster defined by a generic SRAM macro with a single-bit multi-bank cluster, the single-bit multi-bank cluster including a plurality of CiM SRAM cells and a plurality of C-2C capacitor ladder cells, arranging a plurality of single-bit multi-bank clusters to form a multi-bit multi-bank cluster, and arranging a plurality of multi-bit multi-bank clusters into a multi-dimensional MAC computational unit within a region of the generic SRAM macro, where an output of at least two of the multi-bit multi-bank clusters are electrically coupled to form an output analog activation line, and where a plurality of bit lines and a plurality of word lines remain at the same grid locations as provided in the generic SRAM macro. Embodiments include arranging a plurality of multi-dimensional MAC computational units into an in-memory MAC computing array.