公开(公告)号：US20240120651A1

公开(公告)日：2024-04-11

申请号：US17957752

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Zhen Zhou ,  Tae Young Yang ,  Timo Huusari ,  Renzhi Liu ,  Wei Qian ,  Mengyuan Huang ,  Jason Mix

IPC: H01Q3/26 ,  H01L23/498 ,  H01L23/66

CPC classification number: H01Q3/2676 ,  H01L23/49827 ,  H01L23/66 ,  H01L2223/6677

Abstract: Photonically steered impedance surface antennas are disclosed. A disclosed example apparatus includes a semiconductor substrate to be communicatively coupled to a radio frequency (RF) source, an at least partially transparent dielectric layer, the semiconductor substrate at a first side of the at least partially transparent dielectric layer, an at least partially transparent conductive film at a second side of the at least partially transparent dielectric layer that is opposite the first side of the at least partially transparent dielectric layer, and an illumination source to illuminate at least a portion of the semiconductor substrate to generate a photoinduced solid-state plasma pattern that beam steers an RF signal corresponding to the RF source.

公开(公告)号：US20240020093A1

公开(公告)日：2024-01-18

申请号：US18477716

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Richard Dorrance ,  Deepak Dasalukunte ,  Renzhi Liu ,  Hechen Wang ,  Brent Carlton

IPC: G06F7/483

CPC classification number: G06F7/483

Abstract: Systems, apparatuses and methods include technology that identifies workload numbers associated with a workload. The technology converts the workload numbers to block floating point numbers based on a division of mantissas of the workload numbers into sub-words and executes a compute-in memory operation based on the sub-words to generate partial products.

公开(公告)号：US11044671B2

公开(公告)日：2021-06-22

申请号：US16369953

申请日：2019-03-29

Applicant: Intel Corporation

Inventor： Renzhi Liu ,  Asma Beevi Kuriparambil Thekkumpate ,  Brent Carlton

IPC: H04W52/02 ,  H04W84/12 ,  H04W88/02

Abstract: A communication device can include a receiver frontend and a wake-up receiver (WUR) frontend. The receiver frontend can have a radio frequency (RF) interface configured to couple to an antenna and a baseband interface configured to couple to a baseband component. The WUR frontend can be selectively coupled to the receiver frontend (e.g. between the RF interface and the baseband interface). The WUR frontend may monitor a communication channel and control the receiver frontend to adjust its operating mode (e.g. waking the receiver frontend from a sleep mode) based on the monitoring. The WUR frontend may have a lower power consumption than the receiver frontend. The WUR frontend and the receiver frontend may share the same impedance matching network and/or the RF interface.

公开(公告)号：US12009321B2

公开(公告)日：2024-06-11

申请号：US17131863

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Zhen Zhou ,  Tae Young Yang ,  Tolga Acikalin ,  Johanny Escobar Pelaez ,  Kenneth P. Foust ,  Chia-Pin Chiu ,  Renzhi Liu ,  Cheng-Yuan Chin

IPC: H01L23/66 ,  H01L23/14 ,  H01L29/93 ,  H01Q1/22 ,  H01Q1/42 ,  H01Q15/00 ,  H01Q15/14

CPC classification number: H01L23/66 ,  H01L23/14 ,  H01L29/93 ,  H01Q1/2283 ,  H01Q1/422 ,  H01Q15/002 ,  H01Q15/0026 ,  H01Q15/147 ,  H01L2223/6627 ,  H01L2223/6677

Abstract: In various aspects, a package system includes at least a first package and a second package arranged on a same side of the package carrier. Each of the first package and the second package comprises an antenna to transmit and/or receive radio frequency signals. A cover may be arranged at a distance over the first package and the second package at the same side of the package carrier as the first package and the second package. The cover comprises at least one conductive element forming a predefined pattern on a side of the cover facing the first package and the second package. The predefined pattern is configured as a frequency selective surface. The package system further includes a radio frequency signal interface wirelessly connecting the antennas of the first package and the second package. The radio frequency signal interface comprises the at least one conductive element.

公开(公告)号：US20230161559A1

公开(公告)日：2023-05-25

申请号：US18159220

申请日：2023-01-25

Applicant: Intel Corporation

Inventor： Hechen Wang ,  Renzhi Liu ,  Richard Dorrance ,  Deepak Dasalukunte ,  Brent Carlton

IPC: G06F7/544 ,  G06F7/48 ,  H03M1/78 ,  H03M1/46

CPC classification number: G06F7/5443 ,  G06F7/4824 ,  H03M1/78 ,  H03M1/462

Abstract: Systems, apparatuses and methods may provide for technology that conducts, by a differential signal path, signed multiply-accumulate (MAC) operations on first analog signals and multibit weight data stored in the differential signal path, and outputs, by the differential signal path, second analog signals based on the signed MAC operations.

公开(公告)号：US20220406392A1

公开(公告)日：2022-12-22

申请号：US17353493

申请日：2021-06-21

Applicant: Intel Corporation

Inventor： Hechen Wang ,  Richard Dorrance ,  Renzhi Liu ,  Deepak Dasalukunte

IPC: G11C27/02 ,  G06N3/063

Abstract: Various embodiments provide apparatuses, systems, and methods for multibit analog representation, e.g., for in-memory computing. Embodiments may include a single-ended or differential ladder network to generate an analog value (e.g., a voltage or charge) based on a set of bits from a memory array. The ladder network may include a plurality of branches coupled to an output line, wherein individual branches include a capacitor with a first terminal coupled to the output line and a switch coupled to a second terminal of the capacitor. The switch may be controlled by a respective bit of the set of bits to selectively couple the second terminal of the capacitor to a first voltage node or a second voltage node based on a value of the respective bit. Other embodiments may be described and claimed.

公开(公告)号：US12154638B2

公开(公告)日：2024-11-26

申请号：US17353493

申请日：2021-06-21

Applicant: Intel Corporation

Inventor： Hechen Wang ,  Richard Dorrance ,  Renzhi Liu ,  Deepak Dasalukunte

IPC: G11C27/02 ,  G06N3/063

Abstract: Various embodiments provide apparatuses, systems, and methods for multibit analog representation, e.g., for in-memory computing. Embodiments may include a single-ended or differential ladder network to generate an analog value (e.g., a voltage or charge) based on a set of bits from a memory array. The ladder network may include a plurality of branches coupled to an output line, wherein individual branches include a capacitor with a first terminal coupled to the output line and a switch coupled to a second terminal of the capacitor. The switch may be controlled by a respective bit of the set of bits to selectively couple the second terminal of the capacitor to a first voltage node or a second voltage node based on a value of the respective bit. Other embodiments may be described and claimed.

公开(公告)号：US20230251943A1

公开(公告)日：2023-08-10

申请号：US18298906

申请日：2023-04-11

Applicant: Intel Corporation

Inventor： Richard Dorrance ,  Renzhi Liu ,  Hechen Wang ,  Deepak Dasalukunte ,  Brent Carlton

IPC: G06F11/20

CPC classification number: G06F11/2041

Abstract: Systems, apparatuses and methods may provide for technology that includes a plurality of analog to digital converters (ADCs), compute-in-memory (CiM) multiply-accumulate (MAC) hardware coupled to the plurality of ADCs, and a plurality of digital to analog converters (DACs) coupled to the CiM MAC hardware, wherein the plurality of DACs includes one or more redundant DACs. In one example, the technology uses a DAC disconnect scheme to statically bypass defective memory bitcells and compute capacitors to improve yield with minimal overhead, and dynamically boost the effective precision of the ADC in the presence of weight/activation sparsity in neural network (NN) compute.

公开(公告)号：US20220416428A1

公开(公告)日：2022-12-29

申请号：US17357658

申请日：2021-06-24

Applicant: Intel Corporation

Inventor： Zhen Zhou ,  Tae Young Yang ,  Shuhei Yamada ,  Tolga Acikalin ,  Johanny Escobar Pelaez ,  Kenneth Foust ,  Jason Mix ,  Renzhi Liu

IPC: H01Q9/04 ,  H01Q1/22

Abstract: Various embodiments provide systems, devices, and methods for an antenna assembly included in an integrated circuit (IC) package. The antenna assembly may be used for near field wireless communication such as package-to-package and/or chip-to-chip communication. The antenna assembly may include a feed plate (e.g., a top feed) that is capacitively coupled to a first via and a second via. The feed plate may further be capacitively coupled to a loading structure. The first via may be conductively coupled to a ground potential. In some embodiments, the antenna assembly may further include a stub structure (e.g., an open stub or a short stub) that is conductively coupled to the second via. An impedance matching network may be coupled between the feed plate and an IC die that communicates using the antenna assembly. Other embodiments may be described and claimed.

公开(公告)号：US20220334801A1

公开(公告)日：2022-10-20

申请号：US17855097

申请日：2022-06-30

Applicant: Intel Corporation

Inventor： Hechen Wang ,  Renzhi Liu ,  Richard Dorrance ,  Deepak Dasalukunte ,  Shigeki Tomishima

IPC: G06F7/523 ,  G06F7/50

Abstract: Systems, apparatuses, and methods include technology that identifies that a first memory cell of a plurality of memory cells stores data that is associated with a multiply-accumulate operation. The plurality of memory cells is associated with a multiply-accumulator (MAC). The technology executes a connection operation to electrically connect the first memory cell to the MAC to execute the multiply-accumulate operation. A second memory cell of the plurality of memory cells is electrically disconnected from the MAC during the multiply-accumulate operation. The technology executes, with the MAC, the multiply-accumulate operation based on the data.