公开(公告)号：US20190319782A1

公开(公告)日：2019-10-17

申请号：US16455950

申请日：2019-06-28

Applicant: Intel Corporation

Inventor： SANTOSH GHOSH ,  Vikram Suresh ,  Sanu Mathew ,  Manoj Sastry ,  Andrew H. Reinders ,  Raghavan Kumar ,  Rafael Misoczki

IPC: H04L9/06 ,  H04L9/32 ,  G06F9/30 ,  G06F7/503

Abstract: In one example an apparatus comprises a computer readable memory, an XMSS operations logic to manage XMSS functions, a chain function controller to manage chain function algorithms, a secure hash algorithm-2 (SHA2) accelerator, a secure hash algorithm-3 (SHA3) accelerator, and a register bank shared between the SHA2 accelerator and the SHA3 accelerator. Other examples may be described.

公开(公告)号：US20170061832A1

公开(公告)日：2017-03-02

申请号：US14752873

申请日：2015-06-27

Applicant: Intel Corporation

Inventor： SANTOSH GHOSH ,  LI ZHAO ,  MANOJ R. SASTRY

IPC: G09C1/00 ,  H04L9/06

CPC classification number: G09C1/00 ,  H04L9/0631 ,  H04L2209/122

Abstract: One embodiment provides an apparatus. The apparatus includes a lightweight cryptographic engine (LCE), the LCE is optimized and has an associated throughput greater than or equal to a target throughput.

Abstract translation: 一个实施例提供一种装置。 该装置包括轻量级加密引擎（LCE），LCE被优化并且具有大于或等于目标吞吐量的相关联吞吐量。