-
公开(公告)号：US20240211253A1
公开(公告)日：2024-06-27
申请号：US18145744
申请日：2022-12-22
Applicant: Intel Corporation
Inventor： Santosh Ghosh , Christoph Dobraunig , Manoj Sastry , Andrew H. Reinders , Regev Shemy , Qian Wang , Rotem Ohana Peretz , Wing Shek Wong , Wajdi Feghali
CPC classification number: G06F9/30029 , G06F9/3016 , G06F9/3802
Abstract: A method comprises fetching, by fetch circuitry, an encoded parity instruction comprising at least one opcode, a first source identifier for a first source, a second source identifier for a second source, a third source identifier for a third source, and a destination identifier for a destination, decoding, by decode circuitry, the encoded parity instruction to generate a decoded parity instruction; and executing, by execution circuitry, the decoded parity instruction to retrieve operands representing a first register from the first source, a second register from the second source, a third register from the third source, and an index from the third source, perform an XOR operation of four words of data from the first register and single word of data from the second register in a position represented by the index to generate a parity value, and store the parity value in a the first register in a position represented by the index.
-
公开(公告)号：US20220247561A1
公开(公告)日：2022-08-04
申请号：US17699830
申请日：2022-03-21
Applicant: Intel Corporation
Inventor： Santosh Ghosh , Andrew H. Reinders , Manoj Sastry
IPC: H04L9/30
Abstract: A method comprises fetching, by fetch circuitry, an encoded butterfly instruction comprising an opcode, a first source identifier, a second source identifier, a third source identifier, and two destination identifiers, decoding, by decode circuitry, the decoded butterfly instruction to generate a decoded butterfly instruction, and executing, by execution circuitry, the decoded butterfly instruction to retrieve operands representing a first input polynomial-coefficient from the first source, a second input polynomial-coefficient from the second source, and a primitive nth root of unity from the third source, perform, in an atomic fashion, a butterfly operation to generate a first output polynomial-coefficient and a second output polynomial-coefficient, and store the first output coefficient and the second output coefficient in a register file accessible to the execution circuitry.
-
公开(公告)号：US11205017B2
公开(公告)日：2021-12-21
申请号：US16456339
申请日：2019-06-28
Applicant: Intel Corporation
Inventor： Vikram Suresh , Sanu Mathew , Rafael Misoczki , Santosh Ghosh , Raghavan Kumar , Manoj Sastry , Andrew H. Reinders
Abstract: Embodiments are directed to post quantum public key signature operation for reconfigurable circuit devices. An embodiment of an apparatus includes one or more processors; and a reconfigurable circuit device, the reconfigurable circuit device including a dedicated cryptographic hash hardware engine, and a reconfigurable fabric including logic elements (LEs), wherein the one or more processors are to configure the reconfigurable circuit device for public key signature operation, including mapping a state machine for public key generation and verification to the reconfigurable fabric, including mapping one or more cryptographic hash engines to the reconfigurable fabric, and combining the dedicated cryptographic hash hardware engine with the one or more mapped cryptographic hash engines for cryptographic signature generation and verification.
-
公开(公告)号：US11516012B2
公开(公告)日：2022-11-29
申请号：US17144216
申请日：2021-01-08
Applicant: Intel Corporation
Inventor： Santosh Ghosh , Andrew H. Reinders , Sudhir K. Satpathy , Manoj R. Sastry
Abstract: In one embodiment, an apparatus includes a hardware accelerator to execute cryptography operations including a Rivest Shamir Adleman (RSA) operation and an elliptic curve cryptography (ECC) operation. The hardware accelerator may include a multiplier circuit comprising a parallel combinatorial multiplier, and an ECC circuit coupled to the multiplier circuit to execute the ECC operation. The ECC circuit may compute a prime field multiplication using the multiplier circuit and reduce a result of the prime field multiplication in a plurality of addition and subtraction operations for a first type of prime modulus. The hardware accelerator may execute the RSA operation using the multiplier circuit. Other embodiments are described and claimed.
-
公开(公告)号：US11424907B2
公开(公告)日：2022-08-23
申请号：US16911261
申请日：2020-06-24
Applicant: Intel Corporation
Inventor： Santosh Ghosh , Andrew H. Reinders , Joseph Friel , Avinash Laxmisha Varna , Manoj Sastry
Abstract: Embodiments are directed to countermeasures for side-channel attacks on protected sign and key exchange operations. An embodiment of storage mediums includes instructions for commencing a process including an elliptic curve scalar multiplication (ESM) operation including application of a secret scalar value; splitting the secret scalar value into two random scalar values; counting a number of leading ‘0’ bits in the scalar value and skipping the number of leading ‘0’ bits in processing; performing an ESM iteration for each bit of the secret scalar value beginning with a most significant ‘1’ bit of the scalar value including a Point Addition operation and a Point Double operation for each bit on randomized points; performing ESM operation dummy iterations equal to the number of leading ‘0’ bits; and returning an output result for the ESM operation.
-
Patent Agency Ranking
公开(公告)号：US20210409188A1
公开(公告)日：2021-12-30
申请号：US16911261
申请日：2020-06-24
Applicant: Intel Corporation
Inventor： Santosh Ghosh , Andrew H. Reinders , Joseph Friel , Avinash Laxmisha Varna , Manoj Sastry
Abstract: Embodiments are directed to countermeasures for side-channel attacks on protected sign and key exchange operations. An embodiment of storage mediums includes instructions for commencing a process including an elliptic curve scalar multiplication (ESM) operation including application of a secret scalar value; splitting the secret scalar value into two random scalar values; counting a number of leading ‘0’ bits in the scalar value and skipping the number of leading ‘0’ bits in processing; performing an ESM iteration for each bit of the secret scalar value beginning with a most significant ‘1’ bit of the scalar value including a Point Addition operation and a Point Double operation for each bit on randomized points; performing ESM operation dummy iterations equal to the number of leading ‘0’ bits; and returning an output result for the ESM operation.
-
公开(公告)号：US10924276B2
公开(公告)日：2021-02-16
申请号：US15982278
申请日：2018-05-17
Applicant: Intel Corporation
Inventor： Santosh Ghosh , Andrew H. Reinders , Sudhir K. Satpathy , Manoj R. Sastry
Abstract: In one embodiment, an apparatus includes: a hardware accelerator to execute cryptography operations including a Rivest Shamir Adleman (RSA) operation and an elliptic curve cryptography (ECC) operation. The hardware accelerator may include: a multiplier circuit comprising a parallel combinatorial multiplier; and an ECC circuit coupled to the multiplier circuit to execute the ECC operation. The ECC circuit may compute a prime field multiplication using the multiplier circuit and reduce a result of the prime field multiplication in a plurality of addition and subtraction operations for a first type of prime modulus. The hardware accelerator may execute the RSA operation using the multiplier circuit. Other embodiments are described and claimed.
-
公开(公告)号：US11917053B2
公开(公告)日：2024-02-27
申请号：US17707629
申请日：2022-03-29
Applicant: Intel Corporation
Inventor： Santosh Ghosh , Vikram Suresh , Sanu Mathew , Manoj Sastry , Andrew H. Reinders , Raghavan Kumar , Rafael Misoczki
CPC classification number: H04L9/0643 , G06F7/503 , G06F9/3012 , H04L9/3247
Abstract: In one example an apparatus comprises a computer readable memory, an XMSS operations logic to manage XMSS functions, a chain function controller to manage chain function algorithms, a secure hash algorithm-2 (SHA2) accelerator, a secure hash algorithm-3 (SHA3) accelerator, and a register bank shared between the SHA2 accelerator and the SHA3 accelerator. Other examples may be described.
-
公开(公告)号：US11722313B2
公开(公告)日：2023-08-08
申请号：US17014600
申请日：2020-09-08
Applicant: Intel Corporation
Inventor： Rafael Misoczki , Andrew H. Reinders , Santosh Ghosh , Manoj Sastry
CPC classification number: H04L9/3247 , G06N10/00 , H04L9/0618 , H04L9/0825 , H04L9/0852 , H04L9/0877 , H04L9/14 , H04L9/3073 , H04L9/0836 , H04L9/3239
Abstract: An apparatus comprises a plurality of hardware security modules, at least a first hardware security module in the plurality of hardware security modules comprising processing circuitry to generate a first plurality of pairs of cryptographic key pairs comprising a first plurality of private keys and a first plurality of public keys, forward the first plurality of public keys to a remote computing device, receive, from the remote computing device, a first plurality of ciphertexts, wherein each ciphertext in the plurality of ciphertexts represents an encryption of a cryptographic seed with a public key selected from the plurality of public keys, receive, from a subset of hardware security modules in the plurality of hardware security modules, a subset of private keys.
-
公开(公告)号：US20190325166A1
公开(公告)日：2019-10-24
申请号：US16456339
申请日：2019-06-28
Applicant: Intel Corporation
Inventor： Vikram Suresh , Sanu Mathew , Rafael Misoczki , Santosh Ghosh , Raghavan Kumar , Manoj Sastry , Andrew H. Reinders
Abstract: Embodiments are directed to post quantum public key signature operation for reconfigurable circuit devices. An embodiment of an apparatus includes one or more processors; and a reconfigurable circuit device, the reconfigurable circuit device including a dedicated cryptographic hash hardware engine, and a reconfigurable fabric including logic elements (LEs), wherein the one or more processors are to configure the reconfigurable circuit device for public key signature operation, including mapping a state machine for public key generation and verification to the reconfigurable fabric, including mapping one or more cryptographic hash engines to the reconfigurable fabric, and combining the dedicated cryptographic hash hardware engine with the one or more mapped cryptographic hash engines for cryptographic signature generation and verification.
-
-
-
-
-
-
-
-
-
Search Results
21
records
(took 0.015 seconds)
