公开(公告)号：US20210326182A1

公开(公告)日：2021-10-21

申请号：US17220763

申请日：2021-04-01

Applicant: Intel Corporation

Inventor： Ned M. Smith ,  Changzheng Wei ,  Songwu Shen ,  Ziye Yang ,  Junyuan Wang ,  Weigang Li ,  Wenqian Yu

IPC: G06F9/50 ,  G06F21/76

Abstract: Technologies for hybrid acceleration of code include a computing device (100) having a processor (120), a field-programmable gate array (FPGA) (130), and an application-specific integrated circuit (ASIC) (132). The computing device (100) offloads a service request, such as a cryptographic request or a packet processing request, to the FPGA (130). The FPGA (130) performs one or more algorithmic tasks of an algorithm to perform the service request. The FPGA (130) determines one or more primitive tasks associated with an algorithm task and encapsulates each primitive task in a buffer that is accessible by the ASIC (132). The ASIC (132) performs the primitive tasks in response to encapsulation in the buffer, and the FPGA (130) returns results of the algorithm. The primitive operations may include cryptographic primitives such as modular exponentiation, modular multiplicative inverse, and modular multiplication. The results may be returned to the processor (120) or a network interface controller of the computing device (100).

公开(公告)号：US10970119B2

公开(公告)日：2021-04-06

申请号：US15755216

申请日：2017-03-28

Applicant: INTEL CORPORATION

Inventor： Ned M. Smith ,  Changzheng Wei ,  Songwu Shen ,  Ziye Yang ,  Junyuan Wang ,  Weigang Li ,  Wenqian Yu

IPC: G06F9/50 ,  G06F21/76 ,  G06F21/60

Abstract: Technologies for hybrid acceleration of code include a computing device (100) having a processor (120), a field-programmable gate array (FPGA) (130), and an application-specific integrated circuit (ASIC) (132). The computing device (100) offloads a service request, such as a cryptographic request or a packet processing request, to the FPGA (130). The FPGA (130) performs one or more algorithmic tasks of an algorithm to perform the service request. The FPGA (130) determines one or more primitive tasks associated with an algorithm task and encapsulates each primitive task in a buffer that is accessible by the ASIC (132). The ASIC (132) performs the primitive tasks in response to encapsulation in the buffer, and the FPGA (130) returns results of the algorithm. The primitive operations may include cryptographic primitives such as modular exponentiation, modular multiplicative inverse, and modular multiplication. The results may be returned to the processor (120) or a network interface controller of the computing device (100).