公开(公告)号：US5936896A

公开(公告)日：1999-08-10

申请号：US79835

申请日：1998-05-15

Applicant: Il-jae Cho ,  Jin-man Han

Inventor： Il-jae Cho ,  Jin-man Han

IPC: G11C11/417 ,  G11C7/10 ,  G11C11/407 ,  G11C11/409 ,  H03K19/017 ,  G11C7/00

CPC classification number: G11C7/1057 ,  G11C7/1051 ,  G11C7/1078 ,  H03K19/01721

Abstract: A signal line driver operating at high speed and consuming low power and a semiconductor memory device employing the same are disclosed. The signal line driver includes one or more first pull-up transistors, one or more second pull-up transistors, and one or more pull-down transistors. The first pull-up transistor is connected between an external power supply terminal and an output terminal and responds to a first control signal which swings between an internal power supply voltage and a ground voltage. The external power supply terminal receives an external power supply having a voltage level higher than the voltage level of the internal power supply. The first pull-up transistor provides an output signal to the output terminal having the voltage level of the internal power supply voltage minus a predetermined voltage drop. The second pull-up transistor is connected between the internal power supply voltage terminal and the output terminal. The internal power supply terminal receives the internal power supply. The second pull-up transistor increases the voltage level of the output signal to the voltage level of the internal power supply responsive to a second control signal. The pull-down transistor is connected between the output terminal and the ground voltage. The pull-down transistor provides a ground voltage to the output terminal responsive to a third control signal. The semiconductor memory device includes an input buffer, an output buffer, a data input/output line write driver, an input/output line write driver, a data input/output line read driver, and a memory cell array. At least one of the drivers for the semiconductor memory device includes the signal line driver described above.

Abstract translation: 公开了以高速度操作并消耗低功率的信号线驱动器和采用其的半导体存储器件。 信号线驱动器包括一个或多个第一上拉晶体管，一个或多个第二上拉晶体管和一个或多个下拉晶体管。 第一上拉晶体管连接在外部电源端子和输出端子之间，并响应在内部电源电压和接地电压之间摆动的第一控制信号。 外部电源端子接收具有高于内部电源的电压电平的电压电平的外部电源。 第一上拉晶体管向输出端提供具有内部电源电压的电压电平减去预定电压降的输出信号。 第二上拉晶体管连接在内部电源电压端子和输出端子之间。 内部电源端子接收内部电源。 第二上拉晶体管响应于第二控制信号将输出信号的电压电平增加到内部电源的电压电平。 下拉晶体管连接在输出端子和接地电压之间。 下拉晶体管响应于第三控制信号向输出端提供接地电压。 半导体存储器件包括输入缓冲器，输出缓冲器，数据输入/输出线写驱动器，输入/输出线写驱动器，数据输入/输出线读驱动器和存储单元阵列。 用于半导体存储器件的驱动器中的至少一个包括上述信号线驱动器。