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公开(公告)号：US20210158888A1
公开(公告)日：2021-05-27
申请号：US16693126
申请日：2019-11-22
Applicant: Micron Technology, Inc.
Inventor： Christopher G. Wieduwilt , James S. Rehmeyer , Seth A. Eichmeyer
Abstract: Methods, apparatuses and systems related to managing access to a memory device are described. A memory device includes fuses and latches for storing a repair segment locator and a repair address for each repair of one or more defective memory cells. A segment-address determination circuit generate an active segment address based on the repair address according to the repair segment locator and an address for a read or a write operation. A comparator circuitry is configured to determine whether the active segment address matches the address for the read or the write operation for replacing the one or more defective memory cells with the plurality of redundant cells when the address for the read/write operation corresponds to the one or more defective memory cells.
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公开(公告)号：US20250061020A1
公开(公告)日：2025-02-20
申请号：US18778645
申请日：2024-07-19
Applicant: Micron Technology, Inc.
Abstract: Apparatuses, systems, and methods for tracking latch upset events using a trim register are described. An example method includes reading trim data from trim registers in a non-volatile memory device. The example method can further include generating parity data for the trim data. The example method can further include storing the parity data in the trim registers. The example method can further include, subsequent to the generation and storage of the parity data, re-reading the trim data from the trim registers, generating additional parity data, and comparing the parity data to the additional parity data.
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Patent Agency Ranking
公开(公告)号：US11948655B2
公开(公告)日：2024-04-02
申请号：US17726139
申请日：2022-04-21
Applicant: Micron Technology, Inc.
CPC classification number: G11C29/4401 , G11C29/18 , G11C29/787 , H03K19/20 , G11C2029/4402
Abstract: Methods, systems, and devices for indicating a blocked repair operation are described. A first indication of whether an address of a memory device is valid may be stored. After the first indication is stored, a command for accessing the address may be processed. Based on processing the command, a second indication of whether the address is valid may be obtained, and a determination of whether to perform or prevent a repair operation for repairing the address may be made based on the first indication and the second indication. A third indication of whether the repair operation was performed or prevented may be stored.
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公开(公告)号：US20230343409A1
公开(公告)日：2023-10-26
申请号：US17726139
申请日：2022-04-21
Applicant: Micron Technology, Inc.
CPC classification number: G11C29/4401 , G11C29/18 , G11C29/787 , H03K19/20 , G11C2029/4402
Abstract: Methods, systems, and devices for indicating a blocked repair operation are described. A first indication of whether an address of a memory device is valid may be stored. After the first indication is stored, a command for accessing the address may be processed. Based on processing the command, a second indication of whether the address is valid may be obtained, and a determination of whether to perform or prevent a repair operation for repairing the address may be made based on the first indication and the second indication. A third indication of whether the repair operation was performed or prevented may be stored.
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公开(公告)号：US20230222032A1
公开(公告)日：2023-07-13
申请号：US17572129
申请日：2022-01-10
Applicant: Micron Technology, Inc.
Inventor： Matthew D. Jenkinson , Seth A. Eichmeyer , Christopher G. Wieduwilt
CPC classification number: G06F11/1068 , G06F11/076 , G06F11/0772 , G06F11/0793 , G06F11/3037
Abstract: Methods, systems, and devices for error evaluation for a memory system are described. A memory device may be configured to monitor access errors of the memory device to evaluate a likelihood that such errors are related to a failure of the memory device itself or to a failure outside the memory device. For example, a memory device may monitor a respective quantity of errors for each of a set of banks and, if the memory device detects that multiple banks are associated with a threshold quantity of access errors, the memory device may infer the presence of a failure outside the memory device. The memory device may store an indication of such a detection, which may be used to support failure diagnosis or resolution efforts, such as refraining from replacing a memory device when access errors are more likely to be the result of a system failure.
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公开(公告)号：US11468965B2
公开(公告)日：2022-10-11
申请号：US16599796
申请日：2019-10-11
Applicant: Micron Technology, Inc.
Inventor： Seth A. Eichmeyer , Patrick Mullarkey
Abstract: Methods, systems, and devices for programming anti-fuses are described. An apparatus may include a repair array including elements for replacing faulty elements in a memory array and may further include an array of anti-fuses for indicating which, if any, elements of the memory array are being replaced by elements within the repair array. The array of anti-fuses may indicate an address of an element of the memory array being replaced by an element within the repair array. The array of anti-fuses may indicate an enablement or disablement of the element within the repair array indicating whether the element within the repair array is enabled to replace the element of the memory array. The array of anti-fuses may include anti-fuses with lower reliability and anti-fuses with higher reliability. An anti-fuse associated with the enabling of the element within the repair array may include an anti-fuse having the higher reliability.
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公开(公告)号：US20210398603A1
公开(公告)日：2021-12-23
申请号：US17466160
申请日：2021-09-03
Applicant: Micron Technology, Inc.
Inventor： Christopher G. Wieduwilt , James S. Rehmeyer , Seth A. Eichmeyer
Abstract: Methods, apparatuses and systems related to managing repair assets are described. An apparatus stores a repair segment locator and a repair address for each defect repair. The apparatus may be configured to selectively apply a repair asset to one of multiple sections according to the repair segment locator.
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