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公开(公告)号：US20250061017A1
公开(公告)日：2025-02-20
申请号：US18781064
申请日：2024-07-23
Applicant: Micron Technology, Inc.
Abstract: Apparatuses, systems, and methods for correcting latch upset events in a trim register are described. An example method includes sending a command, from a controller, to access at least one block of a plurality of blocks of a non-volatile memory. The method can further include receiving a failure message associated with reading the at least one block. The method can further include, in response to receiving the failure message, resetting trim data associated with the plurality of blocks.
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公开(公告)号：US20210183433A1
公开(公告)日：2021-06-17
申请号：US17186913
申请日：2021-02-26
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Matthew D. Jenkinson , Nathaniel J. Meier , Dennis G. Montierth
IPC: G11C11/406 , G11C11/408
Abstract: Embodiments of the disclosure are drawn to apparatuses, systems, and methods for dynamic refresh allocation. Memories may be subject to row hammer attacks, where one or more wordlines are repeatedly accessed to cause data degradation in victim rows nearby to the hammered wordlines. A memory may perform background auto-refresh operations, and targeted refresh operations where victim wordlines are refreshed. The memory may monitor access patterns to the memory in order to dynamically allocate the number of targeted refresh operations and auto-refresh operations in a set of refresh operations based on if a hammer attack is occurring and the type of hammer attack which is occurring.
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公开(公告)号：US20210057022A1
公开(公告)日：2021-02-25
申请号：US16549411
申请日：2019-08-23
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Matthew D. Jenkinson , Nathaniel J. Meier , Dennis G. Montierth
IPC: G11C11/406 , G11C11/408
Abstract: Embodiments of the disclosure are drawn to apparatuses, systems, and methods for dynamic refresh allocation. Memories may be subject to row hammer attacks, where one or more wordlines are repeatedly accessed to cause data degradation in victim rows nearby to the hammered wordlines. A memory may perform background auto-refresh operations, and targeted refresh operations where victim wordlines are refreshed. The memory may monitor access patterns to the memory in order to dynamically allocate the number of targeted refresh operations and auto-refresh operations in a set of refresh operations based on if a hammer attack is occurring and the type of hammer attack which is occurring.
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公开(公告)号：US20250061058A1
公开(公告)日：2025-02-20
申请号：US18778600
申请日：2024-07-19
Applicant: Micron Technology, Inc.
Abstract: Apparatuses, systems, and methods for block status parity data are described. An example method includes storing block status data associated with at least one block of a non-volatile memory that indicates a status of the at least one block of memory within a controller. The example method further comprises storing parity data that corresponds to the block status data. The example method further comprises prior to writing the block status data to the non-volatile memory, comparing the stored block status data to the parity data.
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公开(公告)号：US20250061016A1
公开(公告)日：2025-02-20
申请号：US18784572
申请日：2024-07-25
Applicant: Micron Technology, Inc.
IPC: G06F11/10
Abstract: Apparatuses, systems, and methods for block status data reset are described. An example method includes sending a command, from a controller, to access at least one block of a first memory device. The example method further comprises receiving a failure message from the first memory device due to the at least one block being tagged as a bad block in block status data of the first memory device. The example method further comprises in response to receiving the failure message, resetting the block status data by reloading previously stored block status data from a second memory device.
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Patent Agency Ranking
公开(公告)号：US11829243B2
公开(公告)日：2023-11-28
申请号：US17572129
申请日：2022-01-10
Applicant: Micron Technology, Inc.
Inventor： Matthew D. Jenkinson , Seth A. Eichmeyer , Christopher G. Wieduwilt
CPC classification number: G06F11/1068 , G06F11/076 , G06F11/0772 , G06F11/0793 , G06F11/3037
Abstract: Methods, systems, and devices for error evaluation for a memory system are described. A memory device may be configured to monitor access errors of the memory device to evaluate a likelihood that such errors are related to a failure of the memory device itself or to a failure outside the memory device. For example, a memory device may monitor a respective quantity of errors for each of a set of banks and, if the memory device detects that multiple banks are associated with a threshold quantity of access errors, the memory device may infer the presence of a failure outside the memory device. The memory device may store an indication of such a detection, which may be used to support failure diagnosis or resolution efforts, such as refraining from replacing a memory device when access errors are more likely to be the result of a system failure.
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公开(公告)号：US20250060893A1
公开(公告)日：2025-02-20
申请号：US18781102
申请日：2024-07-23
Applicant: Micron Technology, Inc.
IPC: G06F3/06
Abstract: Apparatuses, systems, and methods for tracking latch upset events using block status data are described. An example method includes tracking a block status of each of a plurality of blocks of a first memory device by storing a first set of block status data that indicates a status of each block of the plurality of blocks in the first memory device and storing a second set of block status data that indicates a status of each block of the plurality of blocks in a location. The example method further includes comparing the first set of block status data to the second set of block status data.
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公开(公告)号：US12223099B2
公开(公告)日：2025-02-11
申请号：US17706410
申请日：2022-03-28
Applicant: Micron Technology, Inc.
Inventor： Seth A. Eichmeyer , Christopher G. Wieduwilt , Matthew D. Jenkinson
Abstract: A memory device includes a plurality of fuse banks for a memory region. Each fuse bank stores bit information that relates to at least one of a default address for the plurality of fuse banks or an address of a memory cell that is defective. A default address protection circuit is configured to provide a default address status signal indicating whether a fuse bank in the plurality of fuse banks is storing bit information that corresponds to both the default address and an address of a memory cell that is defective. The memory device include a no_match circuit that overrides a repair of the external memory address if the external address matches the default address and if the default address status signal indicates that no fuse bank is storing bit information that corresponds to both the default address and an address of a memory cell that is defective.
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公开(公告)号：US11798610B2
公开(公告)日：2023-10-24
申请号：US17347957
申请日：2021-06-15
Applicant: Micron Technology, Inc.
Inventor： Timothy B. Cowles , Jiyun Li , Beau D. Barry , Matthew D. Jenkinson , Nathaniel J. Meier , Michael A. Shore , Adam J. Grenzebach , Dennis G. Montierth
IPC: G11C11/401 , G11C11/406 , G11C11/408
CPC classification number: G11C11/40611 , G11C11/4085 , G11C11/4087 , G11C11/40618
Abstract: An apparatus may include a refresh control circuit with multiple timing circuits. The timing circuits may be used to control steal rates, e.g., the rate of refresh time slots dedicated to healing victim word lines of row hammers. The timing circuits may be controlled to allow independent adjustment of the steal rates for different victim word lines. Thus, different victim word lines may be refreshed at different rates and the different rates may be independent of one another.
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公开(公告)号：US20230315918A1
公开(公告)日：2023-10-05
申请号：US17706410
申请日：2022-03-28
Applicant: Micron Technology, Inc.
Inventor： Seth A. Eichmeyer , Christopher G. Wieduwilt , Matthew D. Jenkinson
Abstract: A memory device includes a plurality of fuse banks for a memory region. Each fuse bank stores bit information that relates to at least one of a default address for the plurality of fuse banks or an address of a memory cell that is defective. A default address protection circuit is configured to provide a default address status signal indicating whether a fuse bank in the plurality of fuse banks is storing bit information that corresponds to both the default address and an address of a memory cell that is defective. The memory device include a no_match circuit that overrides a repair of the external memory address if the external address matches the default address and if the default address status signal indicates that no fuse bank is storing bit information that corresponds to both the default address and an address of a memory cell that is defective.
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