Register File Bypass With Optional Results Storage and Separate Predication Register File in a VLIW Processor
    21.
    发明申请
    Register File Bypass With Optional Results Storage and Separate Predication Register File in a VLIW Processor 有权
    在VLIW处理器中使用可选结果注册文件旁路存储和分离预测寄存器文件

    公开(公告)号:US20080016327A1

    公开(公告)日:2008-01-17

    申请号:US11769191

    申请日:2007-06-27

    IPC分类号: G06F9/30

    摘要: This invention makes each register bypass forwarding register explicitly addressable in software. Software chooses whether to access the forwarding register immediately eliminating the need for complex automatic detection. Each instruction executes and always writes its result into the forwarding register. Writing this data into the register file in the next cycle is optional as selected by the destination register file number. This invention separates registers storing predication data from the register file. This separation removes the speed problem by enabling scheduling of the predication computation out of the critical path.

    摘要翻译: 本发明使每个寄存器旁路转发寄存器能够在软件中明确地寻址。 软件选择是否立即访问转发寄存器,无需复杂的自动检测。 每个指令执行并且始终将其结果写入转发寄存器。 在下一个周期中将该数据写入寄存器文件是可选的,由目标寄存器文件编号选择。 本发明分离从寄存器文件存储预测数据的寄存器。 这种分离通过使关键路径中的预测计算能够调度来消除速度问题。