公开(公告)号：US20190220278A1

公开(公告)日：2019-07-18

申请号：US16367216

申请日：2019-03-27

申请人： MENACHEM ADELMAN ,  ROBERT VALENTINE ,  BARUKH ZIV ,  AMIT GRADSTEIN ,  SIMON RUBANOVITCH ,  ALEXANDER HEINECKE ,  EVANGELOS GEORGANAS

发明人： MENACHEM ADELMAN ,  ROBERT VALENTINE ,  BARUKH ZIV ,  AMIT GRADSTEIN ,  SIMON RUBANOVITCH ,  ALEXANDER HEINECKE ,  EVANGELOS GEORGANAS

IPC分类号： G06F9/30 ,  G06F7/483

CPC分类号： G06F9/30036 ,  G06F7/483 ,  G06F9/3013 ,  G06F9/30145

摘要： An apparatus and method down-converting and interleaving data elements. For example, one embodiment of a processor comprises: a decoder to decode a first instruction to generate a decoded instruction; a first source register to store a first plurality of packed data elements; a second source register to store a second plurality of packed data elements; a destination register to store a third plurality and a fourth plurality of packed data elements, each of the third and fourth plurality of packed data elements to be encoded with fewer bits than each of the first and second plurality of packed data elements; execution circuitry to execute the decoded instruction, the execution circuitry comprising: down-conversion circuitry to down-convert each of the first plurality of packed data elements to generate one of the third plurality of packed data elements and to down-convert each of the second plurality of packed data elements to generate one of the fourth plurality of packed data elements; interleave circuitry to interleave the third plurality of packed data elements with the fourth plurality of packed data elements within the destination register.

公开(公告)号：US20190129717A1

公开(公告)日：2019-05-02

申请号：US15800321

申请日：2017-11-01

申请人： International Business Machines Corporation

发明人： Gregory W. Alexander ,  David S. Hutton ,  Christian Jacobi ,  Edward T. Malley ,  Anthony Saporito

IPC分类号： G06F9/30

CPC分类号： G06F9/3013 ,  G06F9/3016 ,  G06F9/30181 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3857

摘要： Embodiments of the invention are directed to methods for handling scratch registers in a processor. The method includes receiving a cracked instruction in an instruction dispatch unit of the processor. The method further includes decoding the cracked instruction into a group of micro-operations. Based on a determination that the instruction group uses a scratch register, determining if the scratch register is used in other groups of micro-operations. Based on a determination that the scratch register is not used in other instruction groups, allocating a physical register for use as the scratch register without creating a mapper entry for the scratch register.

公开(公告)号：US20180329708A1

公开(公告)日：2018-11-15

申请号：US16042957

申请日：2018-07-23

申请人： Microsoft Technology Licensing, LLC

发明人： Douglas C. Burger ,  Aaron L. Smith

IPC分类号： G06F9/30 ,  G06F15/80 ,  G06F9/26 ,  G06F12/0806 ,  G06F11/36 ,  G06F9/52 ,  G06F9/46 ,  G06F9/38 ,  G06F15/78 ,  G06F13/42 ,  G06F9/35 ,  G06F9/345 ,  G06F12/1009 ,  G06F9/32 ,  G06F12/0862 ,  G06F9/355 ,  G06F12/0811 ,  G06F12/0875

CPC分类号： G06F9/3016 ,  G06F9/268 ,  G06F9/30007 ,  G06F9/30021 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/3005 ,  G06F9/30058 ,  G06F9/30072 ,  G06F9/30076 ,  G06F9/30087 ,  G06F9/3009 ,  G06F9/30098 ,  G06F9/30101 ,  G06F9/30105 ,  G06F9/3013 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/30189 ,  G06F9/32 ,  G06F9/321 ,  G06F9/345 ,  G06F9/35 ,  G06F9/355 ,  G06F9/3557 ,  G06F9/3802 ,  G06F9/3804 ,  G06F9/3822 ,  G06F9/3824 ,  G06F9/383 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/3842 ,  G06F9/3848 ,  G06F9/3851 ,  G06F9/3853 ,  G06F9/3855 ,  G06F9/3859 ,  G06F9/3867 ,  G06F9/3891 ,  G06F9/466 ,  G06F9/528 ,  G06F11/36 ,  G06F11/3648 ,  G06F11/3656 ,  G06F12/0806 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/1009 ,  G06F13/4221 ,  G06F15/7867 ,  G06F15/80 ,  G06F15/8007 ,  G06F2212/452 ,  G06F2212/602 ,  G06F2212/604 ,  G06F2212/62 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

摘要： Apparatus and methods are disclosed for nullifying memory store instructions and one or more registers identified in a target field of a nullification instruction. In some examples of the disclosed technology, an apparatus can include memory and one or more block-based processor cores configured to fetch and execute a plurality of instruction blocks. One of the cores can include a control unit configured, based at least in part on receiving a nullification instruction, to obtain an instruction identification for a memory access instruction of a plurality of memory access instructions and a register identification of at least one of a plurality of registers, based on a first and second target fields of the nullification instruction. The at least one register and the memory access instruction associated with the instruction identification are nullified. Based on the nullified memory access instruction, a subsequent memory access instruction is executed.

公开(公告)号：US20180225118A1

公开(公告)日：2018-08-09

申请号：US15943614

申请日：2018-04-02

申请人： Ed Grochowski ,  Hong Wang ,  John P. Shen ,  Perry H. Wang ,  Jamison D. Collins ,  James Held ,  Partha Kundu ,  Raya Leviathan ,  Tin-Fook Ngai

发明人： Ed Grochowski ,  Hong Wang ,  John P. Shen ,  Perry H. Wang ,  Jamison D. Collins ,  James Held ,  Partha Kundu ,  Raya Leviathan ,  Tin-Fook Ngai

IPC分类号： G06F9/30 ,  G06F9/38

CPC分类号： G06F9/30003 ,  G06F9/30087 ,  G06F9/3009 ,  G06F9/30101 ,  G06F9/3013 ,  G06F9/384 ,  G06F9/3851

摘要： A method and system to provide user-level multithreading are disclosed. The method according to the present techniques comprises receiving programming instructions to execute one or more shared resource threads (shreds) via an instruction set architecture (ISA). One or more instruction pointers are configured via the ISA; and the one or more shreds are executed simultaneously with a microprocessor, wherein the microprocessor includes multiple instruction sequencers.

公开(公告)号：US20180189059A1

公开(公告)日：2018-07-05

申请号：US15718486

申请日：2017-09-28

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： JI YONG YOON

IPC分类号： G06F9/30

CPC分类号： G06F9/3013 ,  G06F9/3001 ,  G06F9/30029 ,  G06F9/30189 ,  G06F9/3824 ,  G06F13/16

摘要： A processor includes; a processor core, a register selectively controlled by either external hardware during a first operation mode or the processor core during a second operation mode, and a selection circuit receiving first data provided by the external hardware to the register during the first operation mode and second data provided by the processor core to the register during the second operation mode.

公开(公告)号：US20180173532A1

公开(公告)日：2018-06-21

申请号：US15384451

申请日：2016-12-20

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： Joseph Zbiciak

IPC分类号： G06F9/32 ,  G06F9/38 ,  G06F9/30 ,  G06F12/0815 ,  G06F12/0875 ,  G06F12/0897

CPC分类号： G06F12/0897 ,  G06F9/3001 ,  G06F9/30036 ,  G06F9/30047 ,  G06F9/30072 ,  G06F9/3012 ,  G06F9/3013 ,  G06F9/30145 ,  G06F9/345 ,  G06F9/3822 ,  G06F9/383 ,  G06F9/3853 ,  G06F9/3887 ,  G06F12/0815 ,  G06F12/0862 ,  G06F12/0875 ,  G06F2212/1056 ,  G06F2212/452 ,  G06F2212/454 ,  G06F2212/6026 ,  G06F2212/621

摘要： A streaming engine employed in a digital data processor specifies a fixed read only data stream defined by plural nested loops. An address generator produces address of data elements for the nested loops. A steam head register stores data elements next to be supplied to functional units for use as operands. A stream template register independently specifies a linear address or a circular address mode for each of the nested loops.

公开(公告)号：US09996353B2

公开(公告)日：2018-06-12

申请号：US14632441

申请日：2015-02-26

申请人： International Business Machines Corporation

发明人： Michael J. Genden ,  Hung Q. Le ,  Dung Q. Nguyen ,  Kenneth L. Ward

IPC分类号： G06F9/30 ,  G06F9/38

CPC分类号： G06F9/3013 ,  G06F9/3859 ,  G06F9/3863

摘要： An approach is provided in which a mapper control unit receives first dispatch information corresponding to a first instruction that identifies a first register and a first register type. The mapper control unit dynamically configures a first history buffer entry to support the first register type and, in turn, stores content from the first register into the first history buffer entry. The mapper control unit then receives second dispatch information corresponding to a second instruction that identifies a second register and a second register type, which is different than the first register type. The mapper control unit dynamically configures a second history buffer entry to support the second register type and, in turn, stores content from the second register into the second history buffer entry.

公开(公告)号：US09959118B2

公开(公告)日：2018-05-01

申请号：US15163161

申请日：2016-05-24

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Jonathan D. Bradbury ,  Michael K. Gschwind ,  Christian Jacobi ,  Eric M. Schwarz ,  Timothy J. Slegel

IPC分类号： G06F9/30 ,  G06F9/38 ,  G06F12/0875

CPC分类号： G06F9/30043 ,  G06F9/30036 ,  G06F9/3013 ,  G06F9/3824 ,  G06F12/0875 ,  G06F2212/452

摘要： A Load to Block Boundary instruction is provided that loads a variable number of bytes of data into a register while ensuring that a specified memory boundary is not crossed. The boundary is dynamically determined based on a specified type of boundary and one or more characteristics of the processor executing the instruction, such as cache line size or page size used by the processor.

公开(公告)号：US09952865B2

公开(公告)日：2018-04-24

申请号：US14678944

申请日：2015-04-04

申请人： Texas Instruments Incorporated

发明人： Srinivas Lingam ,  Seok-Jun Lee ,  Johann Zipperer ,  Manish Goel

IPC分类号： G06F9/30 ,  G06F13/16 ,  G06F13/40

CPC分类号： G06F9/3013 ,  G06F9/3001 ,  G06F9/30036 ,  G06F9/30098 ,  G06F9/3877 ,  G06F9/3889 ,  G06F13/1678 ,  G06F13/4018 ,  G06F13/4022 ,  Y02D10/14 ,  Y02D10/151

摘要： An apparatus for a low energy accelerator processor architecture is disclosed. An example arrangement is an integrated circuit that includes a system bus having a data width N, where N is a positive integer; a central processor unit is coupled to the system bus and configured to execute instructions retrieved from a memory; a low energy accelerator processor is configured to execute instruction words received on the system bus and has a plurality of execution units including a load store unit, a load coefficient unit, a multiply unit, and a butterfly/adder ALU unit, wherein each of the execution units is configured to perform operations responsive to retrieved instruction words; and a non-orthogonal data register file comprising a set of data registers coupled to the plurality of execution units, wherein the registers coupled to selected ones of the plurality of execution units. Additional methods and apparatus are disclosed.

公开(公告)号：US09952862B2

公开(公告)日：2018-04-24

申请号：US15163348

申请日：2016-05-24

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Jonathan D. Bradbury ,  Michael K. Gschwind ,  Christian Jacobi ,  Eric M. Schwartz ,  Timothy J. Slegel

IPC分类号： G06F9/30 ,  G06F9/38 ,  G06F12/0875

CPC分类号： G06F9/30043 ,  G06F9/30036 ,  G06F9/3013 ,  G06F9/3824 ,  G06F12/0875 ,  G06F2212/452

摘要： A Load to Block Boundary instruction is provided that loads a variable number of bytes of data into a register while ensuring that a specified memory boundary is not crossed. The boundary is dynamically determined based on a specified type of boundary and one or more characteristics of the processor executing the instruction, such as cache line size or page size used by the processor.