公开(公告)号：US08928511B2

公开(公告)日：2015-01-06

申请号：US13691860

申请日：2012-12-03

Applicant: Mediatek Inc.

Inventor： Yu-Hsin Lin ,  Hung-Chieh Tsai ,  Sheng-Jui Huang

IPC: H03M3/00 ,  H03M7/30

CPC classification number: H03M3/30 ,  H03M3/412 ,  H03M3/426 ,  H03M7/3042

Abstract: A sigma-delta modulator includes a processing circuit, a quantizer, a truncater and a feedback circuit. The processing circuit receives an input signal and an analog information and generates an integrated signal by perform an integration upon a difference between the input signal and the analog information. The quantizer includes a successive approximation register (SAR) analog-to-digital converter (ADC) for receiving the integrated signal and generating a digital information according to the integrated signal. The truncater receives the digital information and generates a truncated information according to the digital information. The feedback circuit generates the analog information to the processing circuit according to the truncated information.

Abstract translation: Σ-Δ调制器包括处理电路，量化器，截短器和反馈电路。 处理电路接收输入信号和模拟信息，并通过根据输入信号和模拟信息之间的差进行积分来产生积分信号。 量化器包括用于接收积分信号并根据积分信号产生数字信息的逐次逼近寄存器（SAR）模拟 - 数字转换器（ADC）。 截断器接收数字信息并根据数字信息产生截断的信息。 反馈电路根据截断的信息向处理电路生成模拟信息。