公开(公告)号：US20210202178A1

公开(公告)日：2021-07-01

申请号：US17131891

申请日：2020-12-23

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Yuta KUROSU ,  Yuta SAITO ,  Masahiro WAKASHIMA ,  Daiki FUKUNAGA ,  Yu TSUTSUI

IPC: H01G4/30 ,  H01G4/012 ,  H01G4/12 ,  H01G4/008 ,  C04B35/468

Abstract: In a multilayer ceramic capacitor, an intersection of an interface is defined by a second dielectric ceramic layer, a first internal electrode layer or a second internal electrode layer, and a third dielectric ceramic layer, on a plane including a length direction and a width direction, the second dielectric ceramic layer and the third dielectric ceramic layer include a near intersection region at or near the intersection, and an average particle size of dielectric particles in the near intersection region is smaller than average particle sizes of dielectric particles in the first dielectric ceramic layer, the second dielectric ceramic layer, and the third dielectric ceramic layer.