公开(公告)号：US4949139A

公开(公告)日：1990-08-14

申请号：US242708

申请日：1988-09-09

申请人： George J. Korsh ,  Edward Hui

发明人： George J. Korsh ,  Edward Hui

IPC分类号： H01L29/423 ,  H03K19/003

CPC分类号： H01L29/4238 ,  H01L29/42396 ,  H03K19/00361

摘要： A transistor construction having a gate electrode meandering in a serpentine manner between interlacked comb-like drain and sources electrodes. The construction is equivalent to parallel transistors with series-connected gates, and the resistivity of the gate electrode forms a RC delay line in which transistors furthest from the gate drivers lag behind those which are closest. Accordingly, the transistor construction turns on or off gradually. The construction is useful as part of a CMOS output driver to memory chips and the like where the inductance of bondwires and the package leads normally cause noise spikes. The transistor construction reduces the current slew rate during switching so that less noise occurs on the chip supply lines. Another embodiment is made up of up to four parallel connected blocks of series-connected-gates. Multiple gate turn-off drivers are provided in a modified output driver, connected in parallel to each series-connected gate block, to insure that the transistor block turns off more rapidly than it turns on.

摘要翻译： 一种晶体管结构，其具有栅极电极，以蛇形方式在嵌入式梳状漏极和源极之间曲折。 该结构相当于具有串联栅极的并联晶体管，栅电极的电阻率形成RC延迟线，其中最远离栅极驱动器的晶体管滞后于最接近晶体管的晶体管。 因此，晶体管结构逐渐打开或关闭。 该结构对于存储芯片等的CMOS输出驱动器的一部分是有用的，其中，焊丝和电感线的电感通常引起噪声尖峰。 晶体管结构降低了切换期间的电流转换速率，从而在芯片供电线路上产生较少的噪声。 另一个实施例由多达四个串联连接的并联连接的块组成。 在修改的输出驱动器中提供多个栅极关断驱动器，并联连接到每个串联连接的栅极块，以确保晶体管块比其导通更快地关断。