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1637 条记录 (耗时 0.028 秒)

    OUTPUT BUFFER CIRCUIT, DATA DRIVER, DISPLAY DEVICE, AND SEMICONDUCTOR DEVICE
    1.
    发明公开
    OUTPUT BUFFER CIRCUIT, DATA DRIVER, DISPLAY DEVICE, AND SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20240321169A1

    公开(公告)日：2024-09-26

    申请号：US18604531

    申请日：2024-03-14

    申请人： LAPIS Technology Co., Ltd.

    发明人： Hiroshi TSUCHI

    IPC分类号： G09G3/20 ,  H03K19/003

    CPC分类号： G09G3/2092 ,  H03K19/00361 ,  G09G2300/0426 ,  G09G2310/0291 ,  G09G2310/08 ,  G09G2330/021 ,  G09G2330/06

    摘要： The disclosure includes: a first transistor, supplying a first power voltage to the output terminal when becoming ON according to a voltage of the input signal received by a gate; a second transistor, supplying a second power voltage to the output terminal in a case of becoming ON in accordance with the voltage of the input signal received by a gate; and an output control part, transitioning to ON by changing a voltage of the gate of the transistor in OFF between the first and second transistors at a change speed based on a current value of a bias current generated by a bias part when the voltage of the input signal changes. According to a voltage change of the input signal, the bias part sets a bias current value to a first value throughout a predetermined period, and switches to a second, lower value in other periods.

    Floating Voltage Suppression in High Speed Multiplexers
    2.
    发明公开
    Floating Voltage Suppression in High Speed Multiplexers 审中-公开

    公开(公告)号：US20240313780A1

    公开(公告)日：2024-09-19

    申请号：US18182996

    申请日：2023-03-13

    申请人： PARADE TECHNOLOGIES, LTD

    发明人： Chieh-Yuan Chao ,  Jenghung Tsai

    IPC分类号： H03K19/173 ,  H03K17/693 ,  H03K19/003 ,  H03K19/1776

    CPC分类号： H03K19/1737 ,  H03K17/693 ,  H03K19/00361 ,  H03K19/1776

    摘要： An electronic device includes two multiplexer branches, a modulation circuit, and an output interface coupled to the modulation circuit and two multiplexer branches. A first multiplexer branch generate s first output signal from a first selection signal, a first inverse signal, and a first input signal. The first inverse signal is substantially complementary to the first selection signal. A second multiplexer branch generates a second output signal from the first selection signal, the first inverse signal, and a second input signal. The modulation circuit generates a logic output signal from the first input signal and the second input signal, independently of the first selection signal and the first inverse signal. The output interface generates a multiplexed signal tracking one of the first input signal and the second input signal based on the first output signal, the second output signal, and the logic output signal.

    INPUT BUFFER WITH HYSTERESIS-INTEGRATED VOLTAGE PROTECTION DEVICES AND RECEIVER INCORPORATING THE INPUT BUFFER
    4.
    发明公开
    INPUT BUFFER WITH HYSTERESIS-INTEGRATED VOLTAGE PROTECTION DEVICES AND RECEIVER INCORPORATING THE INPUT BUFFER 审中-公开

    公开(公告)号：US20240195416A1

    公开(公告)日：2024-06-13

    申请号：US18064978

    申请日：2022-12-13

    申请人： GlobalFoundries U.S. Inc.

    发明人： Dzung T. Tran ,  Deepti A. Pant ,  Shibly S. Ahmed

    IPC分类号： H03K19/003

    CPC分类号： H03K19/00361 ,  H03K19/00315

    摘要： Disclosed is an input buffer with hysteresis-integrated voltage protection devices for avoiding violations of maximum gate-to-source voltage limitations when the maximum input voltage is greater than the maximum gate-to-source voltage limitation. The input buffer includes a chain of transistors including two P-channel FETs (PFETs) and two N-channel FETs (NFETs). The data input to the input buffer controls the gates of the transistors in the chain so the data output from the input buffer at the junction between the PFETs and NFETs is inverted. The input buffer also includes a hysteresis feedback loop to prevent noise-induced switching of the output. The hysteresis feedback loop also includes voltage protection devices integrated therein to avoid maximum gate-to-source violations when the loop results in a hysteresis voltage being fed back into the chain at the source region of a transistor in the chain. Also disclosed is a receiver incorporating the input buffer.

    BIDIRECTIONAL I/O CIRCUIT AND INTEGRATED CIRCUIT INCLUDING BIDIRECTIONAL I/O CIRCUIT
    5.
    发明公开
    BIDIRECTIONAL I/O CIRCUIT AND INTEGRATED CIRCUIT INCLUDING BIDIRECTIONAL I/O CIRCUIT 审中-公开

    公开(公告)号：US20240178839A1

    公开(公告)日：2024-05-30

    申请号：US18483611

    申请日：2023-10-10

    申请人： KEY FOUNDRY CO., LTD.

    发明人： Wanchul KONG ,  Jungho KIM

    IPC分类号： H03K19/003 ,  H03K17/10 ,  H03K19/0185

    CPC分类号： H03K19/00361 ,  H03K17/102 ,  H03K19/018521

    摘要： A bidirectional I/O circuit includes an output post driver configured to control an output signal of a bidirectional pad during a normal mode, a floating N-well network configured to apply a VDD-level bias to the output post driver based on an input signal of the bidirectional pad during a power down mode, and a post driver control circuit configured to set an input voltage level of the output post driver to a VDD level during the power down mode to prevent a leakage current path from being formed through the output post driver. A parasitic diode is formed between the drain of the first PMOS transistor and an N-well of the first PMOS transistor. The N-well of the first PMOS transistor is connected to the floating N-well network, and the source and the N-well of the first PMOS transistor are not physically connected to each other.

    OUTPUT BUFFER CIRCUIT, CHARGE PUMP DEVICE, DISPLAY DRIVE DEVICE, AND DISPLAY DEVICE
    6.
    发明公开
    OUTPUT BUFFER CIRCUIT, CHARGE PUMP DEVICE, DISPLAY DRIVE DEVICE, AND DISPLAY DEVICE 审中-公开

    公开(公告)号：US20240106434A1

    公开(公告)日：2024-03-28

    申请号：US18470380

    申请日：2023-09-19

    申请人： LAPIS Technology Co., Ltd.

    发明人： Hiroshi TSUCHI

    IPC分类号： H03K19/003 ,  G09G3/20

    CPC分类号： H03K19/00361 ,  G09G3/2092 ,  G09G2310/0291 ,  G09G2330/021 ,  G09G2330/028

    摘要： An output buffer circuit includes: a first transistor supplying a first power supply voltage to a first node upon turning on in response to an input signal; a second transistor supplying a second power supply voltage to a second node upon turning on in response to the input signal; a third transistor connecting between the first and second nodes upon turning on in response to a reverse phase signal of a signal on the first node; a fourth transistor connecting between the first and second nodes upon turning on in response to a reverse phase signal of a signal on the second node; a fifth transistor supplying the first power supply voltage upon turning on in response to the signal on the first node; and a sixth transistor supplying the second power supply voltage upon turning on in response to the signal on the second node.

    CURRENT MODE LOGIC CIRCUIT
    9.
    发明公开
    CURRENT MODE LOGIC CIRCUIT 审中-公开

    公开(公告)号：US20230143218A1

    公开(公告)日：2023-05-11

    申请号：US17802555

    申请日：2020-12-09

    申请人： Industry-University Cooperation Foundation Hanyang University

    发明人： Jae Duk HAN

    IPC分类号： H03K19/017 ,  H03K19/003

    CPC分类号： H03K19/01735 ,  H03K19/00384 ,  H03K19/00361

    摘要： According to an aspect, a current mode logic circuit comprise a first transistor to which an input voltage is applied, a second transistor connected in parallel with the first transistor; and a voltage sampling circuit which is connected to the first transistor and the second transistor and resets an output voltage output by integrating the input voltage for a predetermined set time (T) in a manner in which the output voltage is integrated in a direction opposite to a direction in which the input voltage is integrated for the predetermined set time (T).