公开(公告)号：US11425409B2

公开(公告)日：2022-08-23

申请号：US17130298

申请日：2020-12-22

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Takashi Hashimoto ,  Takahiro Nishi ,  Tadamasa Toma ,  Kiyofumi Abe ,  Ryuichi Kanoh

IPC: H04N19/513 ,  H04N19/105 ,  H04N19/176

Abstract: A decoder that decodes a current block using a motion vector includes: a processor; and memory. Using the memory, the processor: derives a first candidate vector from one or more candidate vectors of one or more neighboring blocks that neighbor the current block; determines, in a first reference picture for the current block, a first adjacent region that includes a position indicated by the first candidate vector; calculates evaluation values of a plurality of candidate regions included in the first adjacent region; and determines a first motion vector of the current block, based on a first candidate region having a smallest evaluation value among the evaluation values. The first adjacent region is included in a first motion estimation region determined based on the position indicated by the first candidate vector.

公开(公告)号：US11202093B2

公开(公告)日：2021-12-14

申请号：US16654668

申请日：2019-10-16

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Kiyofumi Abe ,  Takahiro Nishi ,  Tadamasa Toma ,  Ryuichi Kanoh ,  Takashi Hashimoto

IPC: H04N19/573 ,  H04N19/176 ,  H04N19/52

Abstract: An encoder includes memory and circuitry. The circuitry (i) encodes first control information indicating one mode, (ii) encodes second control information indicating whether it is possible to perform the motion compensation in a unit of a sub-block, (iii) derives the motion vector of the block in the one mode, (iv) determines whether to perform the motion compensation in the unit of the sub-block or the motion compensation in a unit of the block, (v) derives a motion vector of the sub-block and performs the motion compensation in the unit of the sub-block using the motion vector of the sub-block when determining to perform the motion compensation in the unit of the sub-block, and (vi) performs the motion compensation in the unit of the block using the motion vector of the block when determining to perform the motion compensation in the unit of the block.

公开(公告)号：US11166020B2

公开(公告)日：2021-11-02

申请号：US16701761

申请日：2019-12-03

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Ryuichi Kanoh ,  Tadamasa Toma ,  Takahiro Nishi ,  Kiyofumi Abe ,  Takashi Hashimoto

IPC: H04N19/117 ,  H04N19/14 ,  H04N19/176 ,  H04N19/196

Abstract: An encoder includes processing circuitry and memory. Using the memory, the processing circuitry: encodes and reconstructs an image to generate a reconstructed image; determines, according to a characteristic of a block in the reconstructed image, an interpolation method for interpolating pixels located outside a referable region including the block; interpolates the pixels located outside the referable region, using the interpolation method determined; and applies a filter to the block using the pixels interpolated.

公开(公告)号：US11064216B2

公开(公告)日：2021-07-13

申请号：US16794944

申请日：2020-02-19

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Kiyofumi Abe ,  Takahiro Nishi ,  Tadamasa Toma ,  Ryuichi Kanoh ,  Takashi Hashimoto

IPC: H04N19/52 ,  H04N19/124 ,  H04N19/159 ,  H04N19/176

Abstract: An encoder includes circuitry and memory. Using the memory, the circuitry, in inter prediction processing: derives a first motion vector of a current block to be processed, using a motion vector of a previous block which has been previously processed; derives a second motion vector of the current block by performing motion estimation in the vicinity of the first motion vector; and generates a prediction image of the current block by performing motion compensation using the second motion vector.

公开(公告)号：US10951896B2

公开(公告)日：2021-03-16

申请号：US16269018

申请日：2019-02-06

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Kiyofumi Abe ,  Takahiro Nishi ,  Takashi Hashimoto ,  Tadamasa Toma

IPC: H04N19/13 ,  H04N19/157 ,  H04N19/91 ,  H04N19/18

Abstract: An encoder includes memory and circuitry accessible to the memory. The circuitry accessible to the memory: switches whether or not to apply arithmetic encoding to a binary data string in which image information has been binarized; binarizes frequency transform coefficient information according to different binarization formats between when arithmetic encoding is applied to the binary data string and when arithmetic encoding is not applied to the binary data string; and binarizes a part or the entirety of prediction parameter information according to a binarization format which is common between when arithmetic encoding is applied to the binary data string and when arithmetic encoding is not applied to the binary data string.

公开(公告)号：US10904527B2

公开(公告)日：2021-01-26

申请号：US16911834

申请日：2020-06-25

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Kiyofumi Abe ,  Takahiro Nishi ,  Takashi Hashimoto ,  Tadamasa Toma

IPC: H04N19/122 ,  H04N19/13 ,  H04N19/146 ,  H04N19/176 ,  H04N19/18 ,  H04N19/61 ,  H04N19/136 ,  H04N19/124 ,  H04N19/159

Abstract: An encoder which encodes image information includes memory and circuitry accessible to the memory. The circuitry binarizes a data value indicating the number of non-zero coefficients included in a current basic block which is one of one or more basic blocks in a frequency transform block, according to a conversion table, to encode the image information which includes the data value. When binarizing the data value, the circuitry selects the conversion table from a plurality of tables including two or more tables which differ from each other in difference between a longest bit length and a shortest bit length of a plurality of binary values associated with a plurality of data values, according to the position of the current basic block in the current frequency transform block which is the frequency transform block including the current basic block, and binarizes the data value according to the conversion table selected.

公开(公告)号：US10742978B2

公开(公告)日：2020-08-11

申请号：US16268979

申请日：2019-02-06

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Kiyofumi Abe ,  Takahiro Nishi ,  Takashi Hashimoto ,  Tadamasa Toma

IPC: H04N19/122 ,  H04N19/13 ,  H04N19/146 ,  H04N19/176 ,  H04N19/18 ,  H04N19/136 ,  H04N19/124 ,  H04N19/159 ,  H04N19/61

Abstract: An encoder which encodes image information includes memory and circuitry accessible to the memory. The circuitry binarizes a data value indicating the number of non-zero coefficients included in a current basic block which is one of one or more basic blocks in a frequency transform block, according to a conversion table, to encode the image information which includes the data value. When binarizing the data value, the circuitry selects the conversion table from a plurality of tables including two or more tables which differ from each other in difference between a longest bit length and a shortest bit length of a plurality of binary values associated with a plurality of data values, according to the position of the current basic block in the current frequency transform block which is the frequency transform block including the current basic block, and binarizes the data value according to the conversion table selected.