公开(公告)号：US5371026A

公开(公告)日：1994-12-06

申请号：US983347

申请日：1992-11-30

申请人： James D. Hayden ,  James R. Pfiester ,  Hsing-Huang Tseng

发明人： James D. Hayden ,  James R. Pfiester ,  Hsing-Huang Tseng

IPC分类号： H01L21/8234 ,  H01L27/088 ,  H01L21/265

CPC分类号： H01L21/823425 ,  H01L27/088

摘要： A semiconductor device (10) and process provides first and second, electrically coupled MOS transistors (14, 16) in which the current gain of the second MOS transistor (16) is greater than the current gain of the first MOS transistor (14). First and second gate structures (23, 25) are formed on a gate dielectric layer (26) overlying a semiconductor substrate (12). The gate dielectric layer (26) has a uniform thickness in all regions. The current gain differential between the first and second MOS transistors (14, 16) is obtained by selectively forming a dielectric intrusion layer (42) under the gate structure (23) of the first MOS transistor (14), whereas the dielectric layer (26) underlying the gate structure (25) of the second MOS transistor (16) retains the uniform thickness. The dielectric intrusion layer (42) causes a higher channel resistance in the first MOS transistor (14) which retards the current gain in the first MOS transistor (14) relative to the current gain of the second MOS transistor ( 16).

摘要翻译： 半导体器件（10）和工艺提供第一和第二电耦合MOS晶体管（14,16），其中第二MOS晶体管（16）的电流增益大于第一MOS晶体管（14）的电流增益。 第一和第二栅极结构（23,25）形成在覆盖半导体衬底（12）的栅极电介质层（26）上。 栅介质层（26）在所有区域中具有均匀的厚度。 通过在第一MOS晶体管（14）的栅极结构（23）下方选择性地形成介质侵入层（42），获得第一和第二MOS晶体管（14,16）之间的电流增益差，而电介质层 ）在第二MOS晶体管（16）的栅极结构（25）下方保持均匀的厚度。 电介质侵入层（42）在第一MOS晶体管（14）中导致相对于第二MOS晶体管（16）的电流增益延迟第一MOS晶体管（14）中的电流增益的较高的沟道电阻。