公开(公告)号：US5830802A

公开(公告)日：1998-11-03

申请号：US521720

申请日：1995-08-31

Applicant: Hsing-Huang Tseng ,  Philip J. Tobin ,  Bikas Maiti

Inventor： Hsing-Huang Tseng ,  Philip J. Tobin ,  Bikas Maiti

IPC: H01L21/28 ,  H01L21/321 ,  H01L21/311

CPC classification number: H01L21/28061 ,  H01L21/321 ,  Y10S148/06 ,  Y10S148/147

Abstract: A process for reducing halogen concentration in a material layer (56) includes the deposition of a dielectric layer (58) overlying the material layer (56). An annealing process is carried out to diffuse halogen atoms from the material layer (56) into the overlying dielectric layer (58). Once the diffusion process is complete, the dielectric layer (58) is removed.

Abstract translation: 用于降低材料层（56）中的卤素浓度的方法包括沉积覆盖在材料层（56）上的介电层（58）。 进行退火处理以将卤素原子从材料层（56）扩散到上覆电介质层（58）中。 一旦扩散过程完成，去除电介质层（58）。

公开(公告)号：US07001852B2

公开(公告)日：2006-02-21

申请号：US10836149

申请日：2004-04-30

Applicant: Tien-Ying Luo ,  Olubunmi O. Adetutu ,  Hsing-Huang Tseng

Inventor： Tien-Ying Luo ,  Olubunmi O. Adetutu ,  Hsing-Huang Tseng

IPC: H01L21/31

CPC classification number: H01L21/02255 ,  H01L21/02299 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28211 ,  H01L21/3141 ,  H01L21/31645 ,  H01L29/513

Abstract: A method of making a high quality thin dielectric layer includes annealing a substrate and a base oxide layer overlying a top surface of the substrate at a first temperature in a first ambient and annealing the substrate and base oxide layer at a second temperature in a second ambient subsequent to the first anneal. The first ambient includes an inert gas ambient selected from the group consisting of a nitrogen, argon, and helium ambient. Prior to the first anneal, the base oxide layer has an initial thickness and an initial density. The first anneal causes a first density and thickness change in the base oxide layer from the initial thickness and density to a first thickness and density, with no incorporation of nitrogen, argon, or helium of the ambient within the base oxide layer. The first thickness is less than the initial thickness and the first density is greater than the initial density. The second anneal causes a second density and thickness change in the base oxide layer from the first thickness and density to a second thickness and density. The second thickness is larger than the first thickness and the second density is on the order of the greater than or equal to the first density.

Abstract translation: 制造高品质薄介电层的方法包括在第一环境中的第一温度下对衬底和覆盖在衬底的顶表面上的基底氧化物层进行退火，并在第二环境中的第二温度退火衬底和基底氧化物层 在第一退火之后。 第一环境包括选自氮，氩和氦环境的惰性气体环境。 在第一退火之前，基底氧化物层具有初始厚度和初始密度。 第一次退火使基底氧化物层中的初始密度和厚度变化从初始厚度和密度到第一厚度和密度，而不会在基底氧化物层内引入环境的氮，氩或氦。 第一厚度小于初始厚度，第一密度大于初始密度。 第二退火导致基础氧化物层中的第二密度和厚度从第一厚度和密度变化到第二厚度和密度。 第二厚度大于第一厚度，第二密度大于或等于第一密度。

公开(公告)号：US6146948A

公开(公告)日：2000-11-14

申请号：US868331

申请日：1997-06-03

Applicant: Wei Edwin Wu ,  Hsing-Huang Tseng ,  Phillip Earl Crabtree ,  Yeong-Jyh Tom Lii

Inventor： Wei Edwin Wu ,  Hsing-Huang Tseng ,  Phillip Earl Crabtree ,  Yeong-Jyh Tom Lii

IPC: H01L21/8234 ,  H01L21/336 ,  H01L21/302 ,  H01L21/461

CPC classification number: H01L21/823462

Abstract: A method for forming a gate dielectric having different thickness begins by providing a substrate (12). A sacrificial oxide (14) is formed overlying the substrate (12). A first portion (11) of the sacrificial oxide (14) is exposed to a carbon-containing plasma environment (20). This carbon-containing plasma environment (20) forms a carbon-containing layer (24) within the region (11). After forming this region (24), a wet etch chemistry (22) is used to remove remaining portions of the sacrificial oxide (14) without forming a layer (24) in the region (13). Furnace oxidation is then used to form regions (26a) and (26b) wherein the growth of region (26a) has been retarded by the presence of the region (24). Therefore, the regions (26a) and (26b) are differing in thickness and can be used to make different transistors having different current gains.

Abstract translation: 用于形成具有不同厚度的栅极电介质的方法从提供衬底（12）开始。 牺牲氧化物（14）形成在衬底（12）上方。 牺牲氧化物（14）的第一部分（11）暴露于含碳等离子体环境（20）中。 该含碳等离子体环境（20）在区域（11）内形成含碳层（24）。 在形成该区域（24）之后，使用湿蚀刻化学品（22）去除牺牲氧化物（14）的剩余部分，而不在区域（13）中形成层（24）。 然后使用炉氧化形成区域（26a）和（26b），其中区域（26a）的生长已被区域（24）的存在延迟。 因此，区域（26a）和（26b）的厚度不同，可用于制造具有不同电流增益的不同晶体管。

公开(公告)号：US5972804A

公开(公告)日：1999-10-26

申请号：US963436

申请日：1997-11-03

Applicant: Philip J. Tobin ,  Rama I. Hegde ,  Hsing-Huang Tseng ,  David O'Meara ,  Victor Wang

Inventor： Philip J. Tobin ,  Rama I. Hegde ,  Hsing-Huang Tseng ,  David O'Meara ,  Victor Wang

IPC: H01L29/78 ,  H01L21/28 ,  H01L21/318 ,  H01L21/336 ,  H01L21/76 ,  H01L29/51 ,  H01L21/285

CPC classification number: H01L21/28202 ,  H01L21/28247 ,  H01L29/518 ,  H01L29/66575 ,  Y10S438/906

Abstract: A method for forming an oxynitride gate dielectric layer (202, 204) begins by providing a semiconductor substrate (200). This semiconductor substrate is cleaned via process steps (10-28). Optional nitridation and oxidation are performed via steps (50 and 60) to form a thin interface layer (202). Bulk oxynitride gate deposition occurs via a step (70) to form a bulk gate dielectric material (204) having custom tailored oxygen and nitrogen profile and concentration. A step (10) is then utilized to in situ cap this bulk dielectric layer (204) with a polysilicon or amorphous silicon layer (208). The layer (208) ensures that the custom tailors oxygen and nitrogen profile and concentration of the underlying gate dielectric (204) is preserved even in the presence of subsequent wafer exposure to oxygen ambients.

Abstract translation: 形成氧氮化物栅极电介质层（202,204）的方法由提供半导体衬底（200）开始。 通过工艺步骤（10-28）清洁该半导体衬底。 通过步骤（50和60）进行可选的氮化和氧化以形成薄界面层（202）。 大量氮氧化物栅极沉积通过步骤（70）发生，以形成具有定制的氧和氮分布和浓度的体栅电介质材料（204）。 然后使用步骤（10）以多晶硅或非晶硅层（208）原位覆盖该体电介质层（204）。 即使在随后的晶片暴露于氧气氛的情况下，层（208）确保定制定制氧气和氮气分布和下层栅极电介质（204）的浓度。

公开(公告)号：US5707889A

公开(公告)日：1998-01-13

申请号：US645362

申请日：1996-05-13

Applicant: Ting Chen Hsu ,  Laureen H. Parker ,  David G. Kolar ,  Philip J. Tobin ,  Hsing-Huang Tseng ,  Lisa K. Garling ,  Vida Ilderem

Inventor： Ting Chen Hsu ,  Laureen H. Parker ,  David G. Kolar ,  Philip J. Tobin ,  Hsing-Huang Tseng ,  Lisa K. Garling ,  Vida Ilderem

IPC: H01L21/32 ,  H01L21/76

CPC classification number: H01L21/32

Abstract: An annealed amorphous silicon layer is formed prior to forming field isolation regions when using in a LOCOS field isolation process. The annealed amorphous silicon layer helps to reduce encroachment compared to conventional LOCOS field isolation process and helps to reduce the likelihood of forming pits within a substrate compared to a PBL field isolation process. The annealed amorphous silicon layer may be used in forming field isolation regions that defines the active regions between transistors including MOSFETs and bipolar transistors. Doped silicon or a silicon-rich silicon nitride layer may be used in place of conventional materials. The anneal of the amorphous silicon layer may be performed after forming a silicon nitride layer if the silicon nitride layer is deposited at a temperature no higher than 600 degrees Celsius.

Abstract translation: 在LOCOS场隔离工艺中使用时，形成退火的非晶硅层，形成场隔离区。 退火的非晶硅层有助于减少与常规LOCOS场隔离过程相比的侵蚀，并且有助于降低与PBL场隔离工艺相比在衬底内形成凹坑的可能性。 退火的非晶硅层可以用于形成场隔离区域，其限定包括MOSFET和双极晶体管的晶体管之间的有源区。 可以使用掺杂硅或富硅的氮化硅层代替常规材料。 如果在不高于600摄氏度的温度下沉积氮化硅层，则可以在形成氮化硅层之后执行非晶硅层的退火。

公开(公告)号：US5436488A

公开(公告)日：1995-07-25

申请号：US332236

申请日：1994-10-31

Applicant: Stephen S. Poon ,  Hsing-Huang Tseng

Inventor： Stephen S. Poon ,  Hsing-Huang Tseng

IPC: H01L21/76 ,  H01L21/762 ,  H01L21/763 ,  H01L27/12

CPC classification number: H01L21/76224 ,  H01L21/763 ,  Y10S148/05

Abstract: The reliability of integrated circuits fabricated with trench isolation is improved by increasing the thickness of the gate dielectric overlying the trench corner. After the trench isolation region (40, 56) has been formed a thin layer of silicon dioxide (44) is chemically vapor deposited over the trench isolation region (44) and the adjacent active region (23). A transistor gate electrode (46) is subsequently formed over the thin layer of silicon dioxide (44). The thin layer of silicon dioxide (44) increases the thickness of the gate dielectric that lies between the transistor gate electrode (46) and the trench corner, and therefore the breakdown voltage of the gate dielectric at the trench corner is increased.

Abstract translation: 通过增加覆盖在沟槽角上的栅极电介质的厚度来提高通过沟槽隔离制造的集成电路的可靠性。 在已经形成沟槽隔离区域（40,56）之后，在沟槽隔离区域（44）和相邻的有源区域（23）上化学气相沉积薄层二氧化硅（44）。 随后在二氧化硅（44）的薄层上形成晶体管栅电极（46）。 二氧化硅（44）的薄层增加位于晶体管栅极（46）和沟槽角之间的栅极电介质的厚度，因此沟槽角处的栅极电介质的击穿电压增加。

公开(公告)号：US06787421B2

公开(公告)日：2004-09-07

申请号：US10219522

申请日：2002-08-15

Applicant: David C. Gilmer ,  Christopher C. Hobbs ,  Hsing-Huang Tseng

Inventor： David C. Gilmer ,  Christopher C. Hobbs ,  Hsing-Huang Tseng

IPC: H01L218234

CPC classification number: H01L21/823462 ,  H01L21/31604 ,  H01L21/3162 ,  H01L28/56 ,  Y10S438/981

Abstract: A semiconductor device (10) having two different gate dielectric thicknesses is formed using a single high-k dielectric layer, preferably a metal oxide. A thicker first gate dielectric (16) is formed in a region of the device for higher voltage requirements, e.g. an I/O region (24). A thinner second gate dielectric (20) is formed in a region of the device for lower voltage requirements, e.g. a core device region (22). First and second dielectrics are preferably silicon dioxide or oxynitride. A metal oxide (26) is deposited over both dielectrics, followed by deposition of a gate electrode material (28). By using a single metal oxide layer in forming the gate dielectric stack for each transistor, together with high quality silicon dioxide or oxynitride dielectric layers, problems associated with selective etching of the metal oxide may be avoided, as may problems associated with various interfaces between the metal oxide and damaged or treated surfaces.

Abstract translation: 具有两个不同栅介质厚度的半导体器件（10）使用单个高k电介质层，优选金属氧化物形成。 在器件的区域中形成较厚的第一栅极电介质（16），用于更高电压要求，例如， I / O区域（24）。 在器件的一个区域中形成较薄的第二栅极电介质（20），用于降低电压要求，例如， 核心设备区域（22）。 第一和第二电介质优选为二氧化硅或氧氮化物。 金属氧化物（26）沉积在两个电介质上，随后沉积栅电极材料（28）。 通过在形成每个晶体管的栅极电介质堆叠中使用单个金属氧化物层以及高质量的二氧化硅或氧氮化物电介质层，可以避免与金属氧化物的选择性蚀刻相关的问题，这可能与在 金属氧化物和损坏或处理过的表面。

公开(公告)号：US5960289A

公开(公告)日：1999-09-28

申请号：US102267

申请日：1998-06-22

Applicant: Paul G. Y. Tsui ,  Hsing-Huang Tseng ,  Navakanta Bhat ,  Ping Chen

Inventor： Paul G. Y. Tsui ,  Hsing-Huang Tseng ,  Navakanta Bhat ,  Ping Chen

IPC: H01L21/8234

CPC classification number: H01L21/823462

Abstract: A method for forming a dual gate oxide (DGO) structure begins by forming a first oxide layer (106) within active areas (110) and (112). A protection layer (108a) is then formed over the layer (106). A mask (114) is used to allow removal of the layers (106 and 108a) from the active area (110). A thermal oxidation process is then used to form a thin second oxide layer (118) within an active area (110). Conductive gate electrodes (120a and 120b) are then formed wherein the first oxide layer (106) and the protection layer (108c) are incorporated into the gate dielectric layer of an MOS transistor (122a). The transistor (122b) has a thinner gate oxide layer that excludes the protection layer (108c).

Abstract translation: 形成双栅极氧化物（DGO）结构的方法开始于在有源区（110）和（112）内形成第一氧化物层（106）。 然后在层（106）上形成保护层（108a）。 掩模（114）用于允许从有源区域（110）移除层（106和108a）。 然后使用热氧化工艺在活性区域（110）内形成薄的第二氧化物层（118）。 然后形成导电栅电极（120a和120b），其中第一氧化物层（106）和保护层（108c）被并入到MOS晶体管（122a）的栅极电介质层中。 晶体管（122b）具有排除保护层（108c）的较薄的栅氧化层。

公开(公告)号：US5712208A

公开(公告)日：1998-01-27

申请号：US449964

申请日：1995-05-25

Applicant: Hsing-Huang Tseng ,  Philip J. Tobin ,  Keith E. Witek

Inventor： Hsing-Huang Tseng ,  Philip J. Tobin ,  Keith E. Witek

IPC: H01L21/28 ,  H01L21/336 ,  H01L29/08 ,  H01L29/51 ,  H01L21/225 ,  H01L21/3115

CPC classification number: H01L29/513 ,  H01L21/28035 ,  H01L21/28176 ,  H01L21/28238 ,  H01L21/28273 ,  H01L29/0847 ,  H01L29/518 ,  H01L29/66575 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28211 ,  Y10S438/923

Abstract: A semiconductor dielectric (10) is formed by providing a base layer (12) having a surface. A thin interface layer (13) is formed at the surface of the base layer (12). The thin interface layer has a substantial concentration of both nitrogen and fluorine. A thermal oxide layer (14) is formed overlying the interface layer (13). A deposited dielectric layer (16) is formed overlying the thermal oxide layer (14). The deposited dielectric layer (16) is optionally densified by a thermal heat cycle. The deposited dielectric layer (16) has micropores that are misaligned to micropores in the thermal oxide layer (14) to provide enhanced features which the nitrogen/fluorine interface further improves the dielectric's features.

Abstract translation: 通过提供具有表面的基底层（12）形成半导体电介质（10）。 在基层（12）的表面形成有薄界面层（13）。 薄界面层具有氮和氟的显着浓度。 在界面层（13）上形成热氧化层（14）。 沉积的介电层（16）形成在热氧化物层（14）上。 沉积的介电层（16）任选地通过热热循环致密化。 沉积的介电层（16）具有与热氧化物层（14）中的微孔不对准的微孔，以提供增强的特征，氮/氟界面进一步改善电介质的特征。

公开(公告)号：US5712177A

公开(公告)日：1998-01-27

申请号：US533496

申请日：1995-09-25

Applicant: Vidya S. Kaushik ,  Hsing-Huang Tseng

Inventor： Vidya S. Kaushik ,  Hsing-Huang Tseng

IPC: H01L21/28 ,  H01L21/8247 ,  H01L29/51 ,  H01L21/316

CPC classification number: H01L21/28185 ,  H01L21/28202 ,  H01L21/28229 ,  H01L21/28273 ,  H01L27/11517 ,  H01L29/513 ,  H01L29/518

Abstract: An embodiment of the invention allows the reversing of the sequence of a stacked gate dielectric layer so that a thermal oxide overlies a CVD deposited oxide. A CVD dielectric (12) is first deposited to a desired thickness. Then a layer of silicon (16), either amorphous or polycrystalline, is deposited overlying the CVD dielectric, wherein this silicon layer is approximately one-half of the desired thickness of the final top oxide. The silicon layer is then thermally oxidized to form thermal oxide (18). This method of the invention allows the denser thermal oxide to be formed overlying the less dense CVD dielectric layer as desired to form a reverse dielectric stack.

Abstract translation: 本发明的一个实施例允许堆叠的栅极电介质层的顺序的反转，使得热氧化物覆盖在CVD沉积的氧化物上。 首先将CVD电介质（12）沉积到期望的厚度。 然后沉积覆盖CVD电介质的无定形或多晶硅层（16），其中该硅层约为最终顶部氧化物所需厚度的一半。 然后将硅层热氧化以形成热氧化物（18）。 本发明的这种方法允许根据需要形成覆盖较不致密的CVD电介质层的更致密的热氧化物以形成反向电介质叠层。