公开(公告)号：US20240179342A1

公开(公告)日：2024-05-30

申请号：US18507544

申请日：2023-11-13

Applicant: QUALCOMM Incorporated

Inventor： Yan Zhang ,  Han Huang ,  Vadim Seregin ,  Marta Karczewicz

IPC: H04N19/52 ,  H04N19/105 ,  H04N19/139 ,  H04N19/176 ,  H04N19/70

CPC classification number: H04N19/52 ,  H04N19/105 ,  H04N19/139 ,  H04N19/176 ,  H04N19/70

Abstract: A video coder is configured to receive a first block of video data to be coded using adaptive affine decoder side motion vector refinement (DMVR). The video coder may determine to set a first motion vector difference (MVD) for a first reference picture list to zero, and then refine control point motion vectors (CPMVs) associated with a second reference picture list to generate refined CPMVs. The video coder may then code the first block of video data using the refined CPMVs.

公开(公告)号：US20240129481A1

公开(公告)日：2024-04-18

申请号：US18471131

申请日：2023-09-20

Applicant: QUALCOMM Incorporated

Inventor： Han Huang ,  Vadim Seregin ,  Marta Karczewicz

IPC: H04N19/139 ,  H04N19/176

CPC classification number: H04N19/139 ,  H04N19/176

Abstract: A video coder may be configured to partition a coding block into subblocks, and generate initial subblock motion vectors for a plurality of the subblocks. The video coder may further refine the initial subblock motion vectors for the plurality of the subblocks using decoder side motion vector refinement to produce refined subblock motion vectors for the plurality of the subblocks, and perform a linear regression on the refined subblock motion vectors and coordinates of the plurality of the subblocks to derive an affine motion model. The video coder may then code the coding block using the derived affine motion model.

公开(公告)号：US20240121426A1

公开(公告)日：2024-04-11

申请号：US18467513

申请日：2023-09-14

Applicant: QUALCOMM Incorporated

Inventor： Han Huang ,  Yan Zhang ,  Zhi Zhang ,  Vadim Seregin ,  Marta Karczewicz

IPC: H04N19/52 ,  H04N19/105 ,  H04N19/119 ,  H04N19/127 ,  H04N19/139 ,  H04N19/159 ,  H04N19/176 ,  H04N19/56

CPC classification number: H04N19/52 ,  H04N19/105 ,  H04N19/119 ,  H04N19/127 ,  H04N19/139 ,  H04N19/159 ,  H04N19/176 ,  H04N19/56

Abstract: Encoding and decoding video data using an affine decoder side motion vector derivation (DMVR) mode includes receiving a block of video data to be decoded using the affine DMVR mode, and dividing the block into a plurality of subblocks. A video encoder and video decoder may determine a final offset for the affine DMVR mode using a first subset of the plurality of subblocks. The video encoder and decoder may code the block of video data using the final offset to generate a coded block of video data.

公开(公告)号：US11924410B2

公开(公告)日：2024-03-05

申请号：US17662140

申请日：2022-05-05

Applicant: QUALCOMM Incorporated

Inventor： Han Huang ,  Yao-Jen Chang ,  Vadim Seregin ,  Chun-Chi Chen ,  Marta Karczewicz

IPC: H04N19/105 ,  H04N19/176 ,  H04N19/51 ,  H04N19/593 ,  H04N19/70

CPC classification number: H04N19/105 ,  H04N19/176 ,  H04N19/51 ,  H04N19/593 ,  H04N19/70

Abstract: An example device for decoding video data includes one or more processors implemented in circuitry and configured to: generate an inter-prediction block for a current block of video data; generate an intra-prediction block for the current block of video data; generate a final prediction block for the current block of video data from the inter-prediction block and the intra-prediction block, including performing each of combined inter/intra prediction (CIIP) mode, overlapped block motion compensation (OBMC), and luma mapping with chroma scaling (LMCS) while generating the final prediction block; and decode the current block of video data using the final prediction block. To generate the final prediction block, the processors may perform LMCS on a first inter-prediction sub-block, combine the LMCS-mapped first inter-prediction sub-block with the intra-prediction block using CIIP, and perform OBMC between the first CIIP prediction block and a second inter-prediction sub-block.

公开(公告)号：US11917141B2

公开(公告)日：2024-02-27

申请号：US17303067

申请日：2021-05-19

Applicant: QUALCOMM Incorporated

Inventor： Nan Hu ,  Vadim Seregin ,  Marta Karczewicz ,  Yong He

IPC: H04N19/117 ,  H04N19/70 ,  H04N19/86 ,  H04N19/80 ,  H04N19/176

CPC classification number: H04N19/117 ,  H04N19/176 ,  H04N19/70 ,  H04N19/80 ,  H04N19/86

Abstract: An example method includes decoding, via a first syntax level of a video bitstream, a first deblocking filter control syntax element with a value that specifies whether deblocking filter information is present in a second syntax level of the bitstream; decoding, via the first syntax level of the bitstream, a second deblocking filter control syntax element with a value that specifies whether deblocking override is enabled; responsive to the first deblocking filter control syntax element specifying that the deblocking filter information is present in the second syntax level of the bitstream and regardless of the value of the second deblocking filter control syntax element, decoding, via the second syntax level, one or more syntax elements that specify deblocking filter information; and applying, based on the deblocking filter information, a deblocking filter to a block of the video data.

公开(公告)号：US20240015333A1

公开(公告)日：2024-01-11

申请号：US18338886

申请日：2023-06-21

Applicant: QUALCOMM Incorporated

Inventor： Chun-Chi Chen ,  Han Huang ,  Vadim Seregin ,  Marta Karczewicz

IPC: H04N19/70 ,  H04N19/176

CPC classification number: H04N19/70 ,  H04N19/176

Abstract: A device for decoding video data comprises one or more processors configured to: obtain a syntax element from a bitstream that includes an encoded representation of the video data; determine, based on the syntax element, that a template-matching tool is enabled; based on the template-matching tool being enabled, applying the template-matching tool to generate a prediction block for a current coding unit (CU) of the video data; and reconstruct the current CU based on the prediction block for the current CU.

公开(公告)号：US20230336713A1

公开(公告)日：2023-10-19

申请号：US18175988

申请日：2023-02-28

Applicant: QUALCOMM Incorporated

Inventor： Han Huang ,  Marta Karczewicz ,  Vadim Seregin

IPC: H04N19/105 ,  H04N19/70

CPC classification number: H04N19/105 ,  H04N19/70

Abstract: Example techniques and devices are disclosed for coding video data. An example device includes memory configured to store the video data and one or more processors implemented in circuitry and communicatively coupled to the memory. The one or more processors are configured to determine that multiple-hypothesis prediction (MHP) is enabled. The one or more processors are configured to, based on determining that MHP is enabled, determine a maximum number of merge candidates for a MHP merge candidate list. The one or more processors are configured to, based on the maximum number of merge candidates for the MHP merge candidate list, determine the MHP merge candidate list. The one or more processors are configured to code the video data based on the MHP merge candidate list.

公开(公告)号：US20230328272A1

公开(公告)日：2023-10-12

申请号：US18177591

申请日：2023-03-02

Applicant: QUALCOMM Incorporated

Inventor： Keming Cao ,  Vadim Seregin ,  Marta Karczewicz

IPC: H04N19/513 ,  H04N19/70

CPC classification number: H04N19/521 ,  H04N19/70

Abstract: A method of encoding or decoding video data includes determining that a block vector difference (BVD) value is non-zero, wherein the BVD value is indicative of a difference between a block vector for a current block of the video data and a block vector predictor, and wherein the block vector points to a reference block based on samples in a same picture as the current block; and encoding or decoding a value for the BVD value, without signaling or parsing syntax information indicating whether an absolute value of the BVD value is greater than one.

公开(公告)号：US20230328244A1

公开(公告)日：2023-10-12

申请号：US18297463

申请日：2023-04-07

Applicant: QUALCOMM Incorporated

Inventor： Bappaditya Ray ,  Vadim Seregin ,  Marta Karczewicz

IPC: H04N19/122 ,  H04N19/176 ,  H04N19/159 ,  H04N19/61 ,  H04N19/18 ,  H04N19/70

CPC classification number: H04N19/122 ,  H04N19/176 ,  H04N19/159 ,  H04N19/61 ,  H04N19/18 ,  H04N19/70

Abstract: A video coder may adaptively determine whether to apply an inter-MTS (multiple transform set) mode to video data. The video coder may adaptively determine one or more of a maximum block size or a minimum block size for applying an inter-MTS mode. The video decoder may determine whether the inter-MTS mode is enabled for a block of video data based on a size of the block compared to one or more of the minimum block size or the maximum block size. and code the block using the inter-MTS mode based on the inter-MTS mode being enabled. Coding the block using the inter-MTS mode includes applying one or more transforms of a plurality of transforms to transform coefficients associated with the block of video data.

公开(公告)号：US11785223B2

公开(公告)日：2023-10-10

申请号：US17321302

申请日：2021-05-14

Applicant: Qualcomm Incorporated

Inventor： Vadim Seregin ,  Wei-Jung Chien ,  Han Huang ,  Marta Karczewicz

IPC: H04N19/433 ,  H04N19/14 ,  H04N19/105 ,  H04N19/176 ,  H04N19/423 ,  H04N19/119

CPC classification number: H04N19/14 ,  H04N19/105 ,  H04N19/119 ,  H04N19/176 ,  H04N19/423

Abstract: A video coder can be configured to code video data by determining a first block size threshold for a block of video data; determining a second block size threshold, wherein the second block size threshold is smaller than the first block size threshold; partitioning the block of video data into smaller sub-blocks; in response to determining that a first partition of the partitioned block is smaller or equal to the first block size threshold, determining that blocks within the partition belong to a parallel estimation area; and in response to determining that a second partition of the partitioned block is smaller or equal to the second block size threshold, determining that blocks within the second partition belong to an area for a shared candidate list.