公开(公告)号：US06249846B1

公开(公告)日：2001-06-19

申请号：US09547163

申请日：2000-04-11

申请人： Stephen Van Doren ,  Rahul Razdan

发明人： Stephen Van Doren ,  Rahul Razdan

IPC分类号： G06F1202

CPC分类号： G06F12/0806 ,  G06F12/0822

摘要： A method and apparatus for preventing system wide data dependent stalls is provided. Requests that reach the top of a probe queue and which target data that is not contained in an attached cache memory, are stalled until the data is filled into the appropriate location in cache memory. Only the associated central processor unit's probe queue is stalled and not the entire system. Accordingly, the present invention allows a system to chain together two or more concurrent operations for the same data block without adversely affecting system performance.

摘要翻译： 提供了一种用于防止系统范围内的数据相关失速的方法和装置。 达到探测队列顶部的请求以及未包含在附加高速缓冲存储器中的目标数据被停止，直到数据被填充到高速缓冲存储器中的适当位置为止。 只有相关联的中央处理器单元的探测队列停滞，而不是整个系统。 因此，本发明允许系统将相同数据块的两个或多个并发操作链接在一起，而不会不利地影响系统性能。

公开(公告)号：US6085294A

公开(公告)日：2000-07-04

申请号：US957129

申请日：1997-10-24

申请人： Stephen Van Doren ,  Rahul Razdan

发明人： Stephen Van Doren ,  Rahul Razdan

IPC分类号： G06F12/08

CPC分类号： G06F12/0806 ,  G06F12/0822

摘要： A method and apparatus for preventing system wide data dependent stalls is provided. Requests that reach the top of a probe queue and which target data that is not contained in an attached cache memory subsystem, are stalled until the data is filled into the appropriate location in cache memory. Only the associated central processor unit's probe queue is stalled and not the entire system. Accordingly, the present invention allows a system to chain together two or more concurrent operations for the same data block without adversely affecting system performance.

摘要翻译： 提供了一种用于防止系统范围内的数据相关失速的方法和装置。 达到探测队列顶部的请求以及连接的高速缓存存储器子系统中未包含的目标数据的请求将停止，直到数据被填充到缓存中的适当位置。 只有相关联的中央处理器单元的探测队列停滞，而不是整个系统。 因此，本发明允许系统将相同数据块的两个或多个并发操作链接在一起，而不会不利地影响系统性能。

公开(公告)号：US5696956A

公开(公告)日：1997-12-09

申请号：US554643

申请日：1995-11-08

申请人： Rahul Razdan ,  Bill Grundmann ,  Michael D. Smith

发明人： Rahul Razdan ,  Bill Grundmann ,  Michael D. Smith

IPC分类号： G06F9/318 ,  G06F9/30

CPC分类号： G06F9/3879 ,  G06F9/30185

摘要： A new class of general purpose computers called Programmable Reduced Instruction Set Computers (PRISC) use RISC techniques a basis for operation. In addition to the conventional RISC instructions, PRISC computers provide hardware programmable resources which can be configured optimally for a given user application. A given user application is compiled using a PRISC compiler which recognizes and evaluates complex instructions into a Boolean expression which is assigned an identifier and stored in conventional memory. The recognition of instructions which may be programmed in hardware is achieved through a combination of bit width analysis and instruction optimization. During execution of the user application on the PRISC computer, the stored expressions are loaded as needed into a programmable functional unit. Once loaded, the expressions are executed during a single instruction cycle.

摘要翻译： 称为可编程精简指令集计算机（PRISC）的新一类通用计算机使用RISC技术作为操作的基础。 除了传统的RISC指令之外，PRISC计算机还提供硬件可编程资源，可以为给定的用户应用程序最佳配置。 使用PRISC编译器编译给定的用户应用程序，PRISC编译器将复杂指令识别并评估为分配了标识符并存储在常规内存中的布尔表达式。 可以通过位宽分析和指令优化的组合来实现可以在硬件中编程的指令的识别。 在PRISC计算机上执行用户应用程序时，所存储的表达式将根据需要加载到可编程功能单元中。 一旦加载，表达式将在单个指令周期内执行。

公开(公告)号：US5694579A

公开(公告)日：1997-12-02

申请号：US019574

申请日：1993-02-18

申请人： Rahul Razdan ,  Gabriel Bischoff

发明人： Rahul Razdan ,  Gabriel Bischoff

IPC分类号： G06F11/26 ,  G06F17/50

CPC分类号： G06F17/5022 ,  G06F11/261

摘要： Computational requirements are reduced for executing simulation code for a logic circuit design having at least some elements which are synchronously clocked by multiple phase clock signals, the logic design being subject to resistive conflicts and to charge sharing, the simulation code including data structures associated with circuit modules and nodes interconnecting the circuit modules. A three-state version of simulation code is generated for the circuit design, the three states corresponding to states 0, 1, or X, where X represents an undefined state. A preanalysis was performed of the three-state version and phase waveforms are stored each representing values occurring at a node of the code. For each phase of a module for which no event-based evaluation need be performed, an appropriate response to an event occurring with respect to the module of the three-state version is determined and stored. A two-state version of simulation code for the circuit design, the two states corresponding to 0, and 1 is generated. For each phase of a module for which no event-based evaluation need be performed, the stored response with respect to corresponding module of the three-state version is determined and stored.

摘要翻译： 对于具有至少一些由多个相位时钟信号同步计时的元件的逻辑电路设计执行仿真代码的计算要求被减少，该逻辑设计受到电阻冲突和电荷共享，该模拟代码包括与电路相关联的数据结构 模块和节点互连电路模块。 为电路设计生成三态版本的仿真代码，这三种状态对应于状态0,1或X，其中X表示未定义状态。 执行三态版本的分析，并且存储每个代表出现在代码节点处的值的相位波形。 对于不需要执行基于事件的评估的模块的每个阶段，确定并存储关于相对于三状态版本的模块发生的事件的适当响应。 电路设计的两状态模拟代码版本，生成对应于0和1的两个状态。 对于不需要执行基于事件的评估的模块的每个阶段，确定并存储关于三态版本的对应模块的存储的响应。

公开(公告)号：US5463561A

公开(公告)日：1995-10-31

申请号：US85639

申请日：1993-06-30

申请人： Rahul Razdan

发明人： Rahul Razdan

IPC分类号： G06F17/50

CPC分类号： G06F17/5022

摘要： A method for determining whether multiple representations of a design of a circuit are consistent with each other, where the circuit includes multiple devices with channels for conducting electrical current. Each representations includes a list of device elements that describe the devices and node elements that describe the nodes which interconnect the devices. The method includes modifying each of the lists by: (1) analyzing the device elements and the node elements to identify at least one channel connected region of said circuit (where a channel connected region includes the subset of the devices that have channels interconnected by a subset of the nodes), (2) defining, for each channel connected region, a channel connected region element that describes the subset of the devices and the subset of the nodes in the region, and (3) replacing the device elements of each subset of devices and the node elements of each subset of nodes in the lists with the channel connected region elements. Thereafter, the modified lists are compared as a basis for determining whether the representations are consistent with each other.

摘要翻译： 一种用于确定电路设计的多个表示是否彼此一致的方法，其中所述电路包括具有用于传导电流的通道的多个设备。 每个表示包括描述描述连接设备的节点的设备和节点元素的设备元素的列表。 该方法包括：通过以下步骤来修改每个列表：（1）分析设备元件和节点元件以识别所述电路的至少一个信道连接区域（其中信道连接区域包括具有通过互连的信道互连的信道的子集 节点的子集），（2）为每个信道连接区域定义描述设备子集和区域中的节点子集的信道连接区域元素，以及（3）替换每个子集的设备元素 的设备和列表中节点的每个子集的节点元素与信道连接的区域元素。 此后，将修改的列表作为确定表示是否彼此一致的基础进行比较。