摘要:
A display controller in a computer system controls the asynchronous output of graphics display data in a computer system having at least one fixed resolution flat panel display. Fixed panel displays may have problems displaying non-native resolutions particularly at lower resolutions. The controller of the present invention uses a time base converter, horizontal and vertical Discrete Time Oscillators (DTO), and polyphase interpolator, which may be Discrete Cosine Transform (DCT)-based to expand graphics display data asynchronously from native resolution to at least one resolution suitable for display on a fixed resolution panel. Graphics data may also be output asynchronously to a CRT. Time base converter receives frequency related input parameters and generates at least one asynchronous output at the desired output resolution.
摘要:
A display controller in a computer system controls the asynchronous output of graphics display data in a computer system having at least one fixed resolution flat panel display. Fixed panel displays may have problems displaying non-native resolutions particularly at lower resolutions. The controller of the present invention uses a time base converter, horizontal and vertical Discrete Time Oscillators (DTO), and polyphase interpolator, which may be Discrete Cosine Transform(DCT)-based to expand graphics display data asynchronously from native resolution to at least one resolution suitable for display on a fixed resolution panel. Graphics data may also be output asynchronously to a CRT. Time base converter receives frequency related input parameters and generates at least one asynchronous output at the desired output resolution.
摘要:
An integrated circuit such as a video controller may be provided with core logic circuitry using CMOS technology which may be operated at different supply voltages such as 3.3 or 5 Volts. At lower supply voltages, the CMOS circuitry may run slower. For a video controller, certain higher resolution, pixel depths, and refresh rates may require high speed operation of the video controller. A monitoring circuit monitors the video mode, pixel resolution, pixel depth, and refresh rate and determines which supply voltage may be used to operate the video controller at such levels. An output signal from the monitoring circuit may be used by a switching circuit to supply an appropriate supply voltage to the integrated circuit. At lower performance levels, the integrated circuit may be operated at lower voltages to conserve power.
摘要:
A television system (TV) with an interlaced display screen for displaying network application data. Pixel data elements representing network application data display are received in a non-interlaced mode. The received data is filtered to reduce sharp transitions in the display. The filtered data is provided in an interlaced format (i.e., only alternate lines of a frame) for display on the television display screen. The interlaced image display is combined with the television signal display by selecting one of them on point by point basis. Flicker is reduced substantially in the final display of network application data due to the filtering.
摘要:
A display controller in a computer system controls the asynchronous output of graphics display data in a computer system having at least one fixed resolution flat panel display. Fixed panel displays may have problems displaying non-native resolutions particularly at lower resolutions. The controller of the present invention uses a time base converter, horizontal and vertical Discrete Time Oscillators (DTO), and polyphase interpolator, which may be Discrete Cosine Transform (DCT)-based to expand graphics display data asynchronously from native resolution to at least one resolution suitable for display on a fixed resolution panel. Graphics data may also be output asynchronously to a CRT. Time base converter receives frequency related input parameters and generates at least one asynchronous output at the desired output resolution.
摘要:
A television system (TV) which enables a user to view display represented by a television signal as well as to access data network applications. The TV includes an on-screen-display (OSD) controller which stores the network application data and other display entities in a memory module as separate bit maps. A single image for display on a TV display screen is generated by overlaying all the display entities (including television signal, network application data, pointer, and low resolution data) according to a predetermined priority. Display entities (other than TV signal) are stored in separate portions of the memory module as independent surfaces to enable the displays of individual display entities to be generated and modified according to the individual display entity requirements.
摘要:
A memory controller for controlling accesses to a memory storing display entities including network application data displayed on a display screen of a television system. For performing a display screen refresh operation, the network application data is retrieved with a predetermined period. Accordingly, the memory controller determines an expected time for receiving the next request for retrieving the network application data for screen refresh. The memory controller blocks any lower priority memory access requests from a few clock cycles prior to the determined expected time. As a result, the requests for retrieving network application data can be serviced in an acceptable time.
摘要:
A television system (TV) with an interlaced display screen for displaying network application data. Pixel data elements representing network application data display are received in a non-interlaced mode. The received data is filtered to reduce sharp transitions in the display. The filtered data is provided in an interlaced format (i.e., only alternate lines of a frame) for display on the television display screen. The interlaced image display is combined with the television signal display by selecting one of them on point by point basis. Flicker is reduced substantially in the final display of network application data due to the filtering.
摘要:
A memory controller for controlling accesses to a memory storing display entities including network application data displayed on a display screen of a television system. For performing a display screen refresh operation, the network application data is retrieved with a predetermined period. Accordingly, the memory controller determines an expected time for receiving the next request for retrieving the network application data for screen refresh. The memory controller bolcks any lower priority memory access requests from a few clock cycles prior to the determined expected time. As a result, the requests for retrieving network application data can be serviced in an acceptable time.
摘要:
A television system (TV) which enables a user to view display represented by a television signal as well as to access data network applications. The TV includes an on-screen-display (OSD) controller which stores the network application data and other display entities in a memory module as separate bit maps. A single image for display on a TV display screen is generated by overlaying all the display entities (including television signal, network application data, pointer, and low resolution data) according to a predetermined priority. Display entities (other than TV signal) are stored in separate portions of the memory module as independent surfaces to enable the displays of individual display entities to be generated and modified according to the individual display entity requirements.