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136 条记录 (耗时 0.035 秒)

    Using a threshold value to control mid-interrupt polling
    22.
    发明授权
    Using a threshold value to control mid-interrupt polling 有权
    使用阈值来控制中间中断轮询

    公开(公告)号：US07788391B2

    公开(公告)日：2010-08-31

    申请号：US10973790

    申请日：2004-10-25

    申请人： Sujoy Sen ,  Anil Vasudevan ,  Linden Cornett ,  Prafulla Deuskar

    发明人： Sujoy Sen ,  Anil Vasudevan ,  Linden Cornett ,  Prafulla Deuskar

    IPC分类号： G06F15/16

    CPC分类号： H04L49/9042 ,  H04L47/50 ,  H04L49/90 ,  H04L69/16 ,  H04L69/161 ,  H04L69/163

    摘要： In one embodiment, a method is provided. The method of this embodiment provides performing packet processing on a packet, and placing the packet in a placement queue; if no read buffer is available, determining if the size of the placement queue exceeds a threshold polling value; and if the size of the placement queue exceeds the threshold polling value: if there are one or more pending DMM (data movement module) requests, polling a DMM to determine if the DMM has completed the one or more pending DMM requests for data associated with an application; and if the DMM has completed the one or more pending DMM requests, then sending a completion notification to the application to receive the data.

    摘要翻译： 在一个实施例中，提供了一种方法。 本实施例的方法提供对分组执行分组处理，并将分组置于放置队列中; 如果没有读取缓冲区可用，则确定布局队列的大小是否超过阈值轮询值; 并且如果布置队列的大小超过阈值轮询值：如果存在一个或多个待处理的DMM（数据移动模块）请求，则轮询DMM以确定DMM是否已经完成了与一个或多个待处理DMM 一个应用程序; 并且如果DMM已经完成了一个或多个待处理的DMM请求，则向应用发送完成通知以接收数据。

    Ordered combination of uncacheable writes
    26.
    发明申请
    Ordered combination of uncacheable writes 审中-公开
    有序的不可写入的组合

    公开(公告)号：US20070156960A1

    公开(公告)日：2007-07-05

    申请号：US11323793

    申请日：2005-12-30

    申请人： Anil Vasudevan ,  Parthasarathy Sarangam ,  Sujoy Sen

    发明人： Anil Vasudevan ,  Parthasarathy Sarangam ,  Sujoy Sen

    IPC分类号： G06F12/00

    CPC分类号： G06F12/0888

    摘要： Methods and apparatus to reduce the number of uncacheable write requests are described. In one embodiment, a single uncacheable write request is sent instead of a plurality of uncacheable write requests to an address.

    摘要翻译： 描述减少不可写入写入请求数量的方法和装置。 在一个实施例中，单个不可缓存的写入请求被发送而不是多个不可缓存的写入请求到地址。

    Techniques to control access to logic
    27.
    发明申请
    Techniques to control access to logic 失效
    控制逻辑访问的技术

    公开(公告)号：US20050238019A1

    公开(公告)日：2005-10-27

    申请号：US11170294

    申请日：2005-06-28

    申请人： Anil Vasudevan ,  Sujoy Sen ,  Nimrod Diamant

    发明人： Anil Vasudevan ,  Sujoy Sen ,  Nimrod Diamant

    IPC分类号： G06F13/28 ,  G06F15/173 ,  H01L29/40 ,  H04L12/56 ,  H04L29/06

    CPC分类号： H04L49/9042 ,  H04L47/50 ,  H04L49/90 ,  H04L69/16 ,  H04L69/161 ,  H04L69/163

    摘要： Techniques are described herein that can be used to control which packets or other data are able to be processed or otherwise utilize logic of a computing device. For example, a signature may be associated with a packet or other data received from a network. The signature and the packet or other data may be transferred to the computing device. Prior to the computing device deciding whether to allow logic such as hardware or software to use, process, or act using the packet or other data, the computing device may inspect the signature to determine if such signature permits such packet or other data to be used, processed, or acted upon.

    摘要翻译： 本文描述了可用于控制哪些分组或其他数据能够被处理或以其他方式利用计算设备的逻辑的技术。 例如，签名可以与从网络接收的分组或其他数据相关联。 签名和分组或其他数据可以被传送到计算设备。 在计算设备决定是否允许诸如硬件或软件的逻辑使用，处理或使用分组或其他数据的操作之前，计算设备可以检查签名以确定这样的签名是否允许使用这样的分组或其他数据 ，处理或采取行动。

    System and method for providing security mechanisms for securing network communication
    28.
    发明授权
    System and method for providing security mechanisms for securing network communication 有权
    提供用于保护网络通信的安全机制的系统和方法

    公开(公告)号：US06915431B1

    公开(公告)日：2005-07-05

    申请号：US09472314

    申请日：1999-12-22

    申请人： Anil Vasudevan ,  Baiju Patel ,  Marc Jalfon

    发明人： Anil Vasudevan ,  Baiju Patel ,  Marc Jalfon

    IPC分类号： G06F11/30 ,  G06F15/16 ,  G06F15/173 ,  G06F15/177 ,  H04L9/00 ,  H04L29/06

    CPC分类号： H04L63/0428 ,  H04L63/06

    摘要： A system and method of providing security mechanisms for securing traffic communicated from a server system to a client system independent of the state of the client system. The server system determines whether the client system has entered an operational state. When the client system is operational, key exchange processes are initiated between the two systems, the results of the key exchange processes being the parameters for use in securing traffic communication between the two systems. The results are stored in the client system. The results are inhibited from being updated in the client system until the server system is successful in completely executing another set of key exchange processes. The results are updated with the results obtained from successful execution of the other set of key exchange processes if the execution of the other set is successful. The traffic communication is thus secured based on whatever results are stored in the client system.

    摘要翻译： 一种提供安全机制的系统和方法，用于保护从服务器系统传递到客户机系统的流量，而与客户端系统的状态无关。 服务器系统确定客户端系统是否已进入运行状态。 当客户端系统运行时，在两个系统之间启动密钥交换过程，密钥交换过程的结果是用于保护两个系统之间的流量通信的参数。 结果存储在客户端系统中。 在客户端系统中禁止结果被更新，直到服务器系统成功完成另一组密钥交换过程。 如果另一组的执行成功，结果将更新成功执行另一组密钥交换过程的结果。 因此，基于客户端系统中存储的任何结果来确保流量通信。

    EFFICIENT RECEIVE INTERRUPT SIGNALING
    30.
    发明申请
    EFFICIENT RECEIVE INTERRUPT SIGNALING 审中-公开

    公开(公告)号：US20200183732A1

    公开(公告)日：2020-06-11

    申请号：US16710556

    申请日：2019-12-11

    申请人： Linden Cornett ,  Anil Vasudevan ,  Parthasarathy Sarangam ,  Kiran Patil

    发明人： Linden Cornett ,  Anil Vasudevan ,  Parthasarathy Sarangam ,  Kiran Patil

    IPC分类号： G06F9/48 ,  G06F9/50

    摘要： Methods for performing efficient receive interrupt signaling and associated apparatus, computing platform, software, and firmware. Receive (RX) queues in which descriptors associated with packets are enqueued are implemented in host memory and logically partitioned into pools, with each RX queue pool associated with a respective interrupt vector. Receive event queues (REQs) associated with respective RX queue pools and interrupt vectors are also implemented in host memory. Event generation is selectively enabled for some RX queues, while event generation is masked for others. In response to event causes for RX queues that are event generation-enabled, associated events are generated and enqueued in the REQs and interrupts on associated interrupt vectors are asserted. The events are serviced by accessing the events in the REQs, which identify the RX queue for the event and a next activity location at which a next descriptor to be processed is located. After asserting an interrupt, an RX queue may be auto-masked to prevent generation of additional events when new descriptors are enqueued in the RX queue.