公开(公告)号：US10510738B2

公开(公告)日：2019-12-17

申请号：US16243469

申请日：2019-01-09

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Kwang-Ho Kim ,  Masaaki Higashitani ,  Fumiaki Toyama ,  Akio Nishida

IPC: H01L23/52 ,  H01L27/11582 ,  H01L25/18 ,  H01L23/00 ,  H01L25/00 ,  H01L23/48 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11565 ,  H01L27/11573 ,  H01L23/522

Abstract: A memory-containing die includes a three-dimensional memory array, a memory dielectric material layer located on a first side of the three-dimensional memory array, and memory-side bonding pads. A logic die includes a peripheral circuitry configured to control operation of the three-dimensional memory array, logic dielectric material layers located on a first side of the peripheral circuitry, and logic-side bonding pads included in the logic dielectric material layers. The logic-side bonding pads includes a pad-level mesh structure electrically connected to a source power supply circuit within the peripheral circuitry and containing an array of discrete openings therethrough, and discrete logic-side bonding pads. The logic-side bonding pads are bonded to a respective one, or a respective subset, of the memory-side bonding pads. The pad-level mesh structure can be used as a component of a source power distribution network.