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公开(公告)号：US11791327B2
公开(公告)日：2023-10-17
申请号：US17411635
申请日：2021-08-25
IPC分类号： H01L25/18 , H01L23/00 , H01L25/00 , H10B43/10 , H10B43/27 , H10B43/35 , H10B43/40 , H10B43/50 , H01L23/48 , H01L23/522 , H10B41/10 , H10B41/27 , H10B41/41
CPC分类号： H01L25/18 , H01L24/08 , H01L24/80 , H01L25/50 , H10B43/10 , H10B43/27 , H10B43/35 , H10B43/40 , H10B43/50 , H01L23/481 , H01L23/5226 , H01L2224/08145 , H01L2224/8083 , H01L2924/1431 , H01L2924/14511 , H10B41/10 , H10B41/27 , H10B41/41
摘要： A memory-containing die includes a three-dimensional memory array, a memory dielectric material layer located on a first side of the three-dimensional memory array, and memory-side bonding pads. A logic die includes a peripheral circuitry configured to control operation of the three-dimensional memory array, logic dielectric material layers located on a first side of the peripheral circuitry, and logic-side bonding pads included in the logic dielectric material layers. The logic-side bonding pads includes a pad-level mesh structure electrically connected to a source power supply circuit within the peripheral circuitry and containing an array of discrete openings therethrough, and discrete logic-side bonding pads. The logic-side bonding pads are bonded to a respective one, or a respective subset, of the memory-side bonding pads. The pad-level mesh structure can be used as a component of a source power distribution network.
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公开(公告)号：US10923496B2
公开(公告)日：2021-02-16
申请号：US16241171
申请日：2019-01-07
IPC分类号： H01L27/11582 , H01L21/8234 , H01L27/11565
摘要： An alternating stack of insulating layers and spacer material layers is formed over a source-level sacrificial layer overlying a substrate. The spacer material layers are formed as, or are subsequently replaced with, electrically conductive layers. Memory stack structures including a respective vertical semiconductor channel and a respective memory film are formed through the alternating stack. A source-level cavity is formed by removing the source-level sacrificial layer. Semiconductor pillar structures may be used to provide mechanical support to the alternating stack during formation of the source-level cavity. A source-level semiconductor material layer can be formed in the source-level cavity. The source-level semiconductor material layer adjoins bottom end portions of the vertical semiconductor channels and laterally surrounds the semiconductor pillar structures. The source-level semiconductor material layer may be electrically isolated from a substrate semiconductor material layer in the substrate by a series connection of two p-n junctions having opposite polarities.
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公开(公告)号：US10797060B2
公开(公告)日：2020-10-06
申请号：US16221894
申请日：2018-12-17
发明人： Rahul Sharangpani , Raghuveer S. Makala , Adarsh Rajashekhar , Fei Zhou , Srikanth Ranganathan , Akio Nishida , Toshihiro Iizuka
IPC分类号： H01L27/11582 , H01L27/11556 , H01L27/11524 , H01L21/8239 , H01L27/1157 , H01L21/8234 , H01L29/08 , H01L29/10
摘要： Three-dimensional memory devices include structures that induce a vertical tensile stress in vertical semiconductor channels to enhance charge carrier mobility. Vertical tensile stress may be induced by a laterally compressive stress applied by stressor pillar structure. The stressor pillar structures can include a stressor material such as a dielectric metal oxide material, silicon nitride, thermal silicon oxide or a semiconductor material having a greater lattice constant than that of the channel. Vertical tensile stress may be induced by a compressive stress applied by electrically conductive layers that laterally surround the vertical semiconductor channel, or by a stress memorization technique that captures a compressive stress from sacrificial material layers. Vertical tensile stress can be generated by a source-level pinning layer that prevents vertical expansion of the vertical semiconductor channel. Vertical tensile stress can be induced by using a layer stack including polysilicon and a silicon-germanium alloy for the vertical semiconductor channel.
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4.发明授权公开(公告)号：US09673304B1
公开(公告)日：2017-06-06
申请号：US15210915
申请日：2016-07-15
发明人： Michiaki Sano , Akira Nakada , Tetsuya Yamada , Manabu Hayashi , Takashi Matsubara , Sung Tae Lee , Akio Nishida
IPC分类号： H01L29/66 , H01L27/115 , H01L29/792 , H01L29/788 , H01L27/11582 , H01L27/11556 , H01L27/24 , H01L45/00
CPC分类号： H01L27/2454 , H01L27/1157 , H01L27/11582 , H01L27/249 , H01L45/04 , H01L45/1226 , H01L45/146
摘要： A method is provided that includes forming a dielectric material above a substrate, forming a hole in the dielectric material, the hole disposed in a first direction, forming a word line layer above the substrate via the hole, the word line layer disposed in a second direction perpendicular to the first direction, forming a nonvolatile memory material on a sidewall of the hole, forming a local bit line in the hole, and forming a memory cell including the nonvolatile memory material at an intersection of the local bit line and the word line layer.
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公开(公告)号：US12101936B2
公开(公告)日：2024-09-24
申请号：US17523487
申请日：2021-11-10
发明人： Tatsuya Hinoue , Yusuke Mukae , Ryousuke Itou , Masanori Tsutsumi , Akio Nishida , Ramy Nashed Bassely Said
IPC分类号： H01L27/11582 , H10B41/27 , H10B43/27
摘要： A method of forming a three-dimensional memory device includes forming an alternating stack of insulating layers and sacrificial material layers over a substrate, forming a memory opening extending through the alternating stack, forming a sacrificial memory opening fill structure in the memory opening, replacing the sacrificial material layers with electrically conductive layers, removing the sacrificial memory opening fill structure selective to the electrically conductive layers, and forming a memory opening fill structure the memory opening after replacing the sacrificial material layers with electrically conductive layers and after removing the sacrificial memory opening fill structure. The memory opening fill structure includes a memory film and a vertical semiconductor channel.
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公开(公告)号：US11587943B2
公开(公告)日：2023-02-21
申请号：US17009374
申请日：2020-09-01
发明人： Masatoshi Nishikawa , Akio Nishida
IPC分类号： H01L25/065 , H01L27/11556 , H01L27/11582 , H01L23/538 , H01L23/00
摘要： A first semiconductor die includes a first substrate, first semiconductor devices, first dielectric material layers having a first silicon oxide surface as an uppermost surface and forming first metal interconnect structures. A second semiconductor die includes a second substrate, second semiconductor devices, and second dielectric material layers forming second metal interconnect structures. A handle substrate is attached to a topmost surface of the second semiconductor die. The second substrate is thinned, and a second silicon oxide surface is provided as a bottommost surface of the second semiconductor die. The second semiconductor die is bonded to the first semiconductor die by inducing oxide-to-oxide bonding between the second silicon oxide surface and the first silicon oxide surface. The handle substrate is detached, and inter-die connection via structures are formed through the second substrate and the bonding interface to contact the first metal interconnect structures. External bonding pads may be subsequently formed.
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公开(公告)号：US11201107B2
公开(公告)日：2021-12-14
申请号：US16829591
申请日：2020-03-25
发明人： Teruo Okina , Akio Nishida , James Kai
IPC分类号： H01L23/48 , H01L25/065 , H01L21/768 , H01L23/00 , H01L27/11582
摘要： A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a carrier substrate. Memory stack structures vertically extend through the alternating stack. Each memory stack structure includes a respective vertical semiconductor channel and a respective memory film. A pass-through via structure vertically extends through a dielectric material portion that is adjacent to the alternating stack. The memory die can be bonded to a logic die containing peripheral circuitry for supporting operations of memory cells within the memory die. A distal end of each of the vertical semiconductor channels is physically exposed by removing the carrier substrate. A source layer is formed directly on the distal end each of the vertical semiconductor channels. A backside bonding pad or bonding wire is formed to be electrically connected to the pass-through via structure.
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公开(公告)号：US10833100B2
公开(公告)日：2020-11-10
申请号：US16816552
申请日：2020-03-12
发明人： Kenji Sugiura , Mitsuteru Mushiga , Yuji Fukano , Akio Nishida
IPC分类号： H01L27/11582 , H01L21/768 , H01L27/11568 , H01L23/522 , H01L27/11556 , H01L27/105 , H01L27/108
摘要： A vertically alternating stack of insulating layers and dielectric spacer material layers is formed over a semiconductor substrate. The vertically alternating stack is patterned into a first alternating stack located at a center region of a memory die and a second alternating stack that laterally encloses the first alternating stack. Memory stack structures are formed through the first alternating stack, and portions of the dielectric spacer material layers in the first alternating stack are replaced with electrically conductive layers while maintaining the second alternating stack intact. At least one metallic wall structure is formed through the second alternating stack. An edge seal assembly is provided, which includes at least one vertical stack of metallic seal structures. Each vertical stack of metallic seal structures vertically extends contiguously from a top surface of the semiconductor substrate to a bonding-side surface of the memory die, and includes a respective metallic wall structure.
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公开(公告)号：US10797062B1
公开(公告)日：2020-10-06
申请号：US16385010
申请日：2019-04-16
发明人： Masatoshi Nishikawa , Akio Nishida
IPC分类号： H01L25/065 , H01L27/11556 , H01L27/11582 , H01L23/538 , H01L23/00
摘要： A first semiconductor die includes a first substrate, first semiconductor devices, first dielectric material layers having a first silicon oxide surface as an uppermost surface and forming first metal interconnect structures. A second semiconductor die includes a second substrate, second semiconductor devices, and second dielectric material layers forming second metal interconnect structures. A handle substrate is attached to a topmost surface of the second semiconductor die. The second substrate is thinned, and a second silicon oxide surface is provided as a bottommost surface of the second semiconductor die. The second semiconductor die is bonded to the first semiconductor die by inducing oxide-to-oxide bonding between the second silicon oxide surface and the first silicon oxide surface. The handle substrate is detached, and inter-die connection via structures are formed through the second substrate and the bonding interface to contact the first metal interconnect structures. External bonding pads may be subsequently formed.
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公开(公告)号：US10354987B1
公开(公告)日：2019-07-16
申请号：US15928340
申请日：2018-03-22
IPC分类号： H01L25/00 , H01L23/48 , H01L23/00 , H01L21/768 , H01L25/18 , H01L27/11582 , H01L27/11556
摘要： Sacrificial pillar structures are formed through a first semiconductor substrate on which first semiconductor devices are subsequently formed. After backside thinning of the first semiconductor substrate, the sacrificial pillar structures are replaced with integrated through-substrate via and pad structures to provide a first semiconductor chip. A second semiconductor chip is provided, which includes a second semiconductor substrate, second semiconductor devices, and second bonding pad structures electrically connected to a respective one of the second semiconductor devices. The first bonding pad structures are bonded to a respective one of the second bonding pad structures by surface activated bonding.
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