公开(公告)号：US08962450B2

公开(公告)日：2015-02-24

申请号：US14049263

申请日：2013-10-09

Applicant: Soitec

Inventor： Patrick Reynaud ,  Sébastien Kerdiles ,  Daniel Delprat

IPC: H01L21/78 ,  H01L21/762

CPC classification number: H01L27/1203 ,  H01L21/76254 ,  H01L29/0649

Abstract: A manufacturing process for a semiconductor-on-insulator structure having reduced electrical losses and which includes a support substrate made of silicon, an oxide layer and a thin layer of semiconductor material, and a polycrystalline silicon layer interleaved between the support substrate and the oxide layer. The process includes a treatment capable of conferring high resistivity to the support substrate prior to formation of the polycrystalline silicon layer, and then conducting at least one long thermal stabilization on the structure at a temperature not exceeding 950° C. for at least 10 minutes.

Abstract translation: 一种具有降低的电损耗的绝缘体上半导体结构的制造方法，其包括由硅，氧化物层和半导体材料薄层制成的支撑衬底，以及在支撑衬底和氧化物层之间交错的多晶硅层 。 该方法包括能够在形成多晶硅层之前赋予支撑衬底高电阻率的处理，然后在不超过950℃的温度下在结构上进行至少一个长的热稳定化至少10分钟。