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    METHOD FOR FABRICATING A STRUCTURE
    6.
    发明申请
    METHOD FOR FABRICATING A STRUCTURE 有权
    制作结构的方法

    公开(公告)号：US20150303247A1

    公开(公告)日：2015-10-22

    申请号：US14646642

    申请日：2013-12-02

    Applicant: Soitec

    Inventor： Alexandre Chibko ,  Isabelle Bertrand ,  Sylvain Peru ,  Sothachett Van ,  Patrick Reynaud

    IPC: H01L29/04 ,  H01L29/16 ,  H01L21/324 ,  H01L21/02

    CPC classification number: H01L29/04 ,  H01L21/02263 ,  H01L21/02524 ,  H01L21/0262 ,  H01L21/02664 ,  H01L21/26506 ,  H01L21/324 ,  H01L21/76254 ,  H01L29/16

    Abstract: This method for fabricating a structure comprising, in succession, a support substrate, a dielectric layer, an active layer, a separator layer of polycrystalline silicon, comprising the steps of: a) providing a donor substrate, b) forming an embrittlement area in the donor substrate, c) providing the support structure, d) forming the separator layer on the support substrate, e) forming the dielectric layer, f) assembling the donor substrate and the support substrate, g) fracturing the donor substrate along the embrittlement area, h) subjecting the structure to a strengthening annealing of at least 10 minutes, the fabrication method being noteworthy in that step d) is executed in such a way that the polycrystalline silicon of the separator layer exhibits an entirely random grain orientation, and in that the strengthening annealing is executed at a temperature strictly greater than 950° C. and less than 1200° C.

    Abstract translation: 用于制造结构的方法包括依次包括支撑衬底，电介质层，有源层，多晶硅隔板层，其包括以下步骤：a）提供施主衬底，b）在所述衬底中形成脆化区域 供体衬底，c）提供支撑结构，d）在支撑衬底上形成隔离层，e）形成电介质层，f）组装供体衬底和支撑衬底，g）沿着脆化区域压裂供体衬底， h）对结构进行至少10分钟的强化退火，在步骤d）中制造方法值得注意的是，隔板层的多晶硅呈现完全随机的晶粒取向， 强化退火在严格高于950℃且小于1200℃的温度下进行。

    Method for manufacturing a semiconductor-on-insulator structure having low electrical losses
    7.
    发明授权
    Method for manufacturing a semiconductor-on-insulator structure having low electrical losses 有权
    具有低电损耗的绝缘体上半导体结构的制造方法

    公开(公告)号：US08962450B2

    公开(公告)日：2015-02-24

    申请号：US14049263

    申请日：2013-10-09

    Applicant: Soitec

    Inventor： Patrick Reynaud ,  Sébastien Kerdiles ,  Daniel Delprat

    IPC: H01L21/78 ,  H01L21/762

    CPC classification number: H01L27/1203 ,  H01L21/76254 ,  H01L29/0649

    Abstract: A manufacturing process for a semiconductor-on-insulator structure having reduced electrical losses and which includes a support substrate made of silicon, an oxide layer and a thin layer of semiconductor material, and a polycrystalline silicon layer interleaved between the support substrate and the oxide layer. The process includes a treatment capable of conferring high resistivity to the support substrate prior to formation of the polycrystalline silicon layer, and then conducting at least one long thermal stabilization on the structure at a temperature not exceeding 950° C. for at least 10 minutes.

    Abstract translation: 一种具有降低的电损耗的绝缘体上半导体结构的制造方法，其包括由硅，氧化物层和半导体材料薄层制成的支撑衬底，以及在支撑衬底和氧化物层之间交错的多晶硅层 。 该方法包括能够在形成多晶硅层之前赋予支撑衬底高电阻率的处理，然后在不超过950℃的温度下在结构上进行至少一个长的热稳定化至少10分钟。

    METHOD OF TESTING A SEMICONDUCTOR ON INSULATOR STRUCTURE AND APPLICATION OF SAID TEST TO THE FABRICATION OF SUCH A STRUCTURE
    8.
    发明申请
    METHOD OF TESTING A SEMICONDUCTOR ON INSULATOR STRUCTURE AND APPLICATION OF SAID TEST TO THE FABRICATION OF SUCH A STRUCTURE 有权
    绝缘子结构半导体测试方法及其测试方法对这种结构的制作

    公开(公告)号：US20150014822A1

    公开(公告)日：2015-01-15

    申请号：US14381537

    申请日：2013-02-18

    Applicant: Soitec

    Inventor： Patrick Reynaud ,  Walter Schwarzenbach ,  Konstantin Bourdelle ,  Jean-Francois Gilbert

    IPC: H01L21/66 ,  G01R31/26

    CPC classification number: H01L22/14 ,  G01R31/2601 ,  H01L22/20

    Abstract: The invention concerns a method of testing a semiconductor on insulator type structure comprising a support substrate, a dielectric layer having a thickness of less than 50 nm and a semiconductor layer, the structure comprising a bonding interface between the dielectric layer and the support substrate or the semiconductor layer or inside the dielectric layer, characterized in that it comprises measuring the charge to breakdown (QBD) of the dielectric layer and in that information is deduced from the measurement relating to the hydrogen concentration in the layer and/or at the bonding interface. The invention also concerns a method of fabricating a batch of semiconductor on insulator type structures including carrying out the test on a sample structure from the batch.

    Abstract translation: 本发明涉及一种测试半导体绝缘体类型结构的方法，包括支撑衬底，厚度小于50nm的电介质层和半导体层，该结构包括介电层和支撑衬底之间的接合界面或 半导体层或电介质层内部，其特征在于，其包括测量电介质层的电荷（QBD），并且从与层中和/或接合界面处的氢浓度相关的测量推导出信息。 本发明还涉及制造一批半导体绝缘体型结构的方法，包括对来自批料的样品结构进行测试。

    Method for manufacturing a semiconductor on insulator structure having low electrical losses
    10.
    发明授权
    Method for manufacturing a semiconductor on insulator structure having low electrical losses 有权
    制造具有低电损耗的绝缘体上半导体结构的方法

    公开(公告)号：US09293473B2

    公开(公告)日：2016-03-22

    申请号：US14612772

    申请日：2015-02-03

    Applicant: Soitec

    Inventor： Patrick Reynaud ,  Sebastien Kerdiles ,  Daniel Delprat

    IPC: H01L27/12 ,  H01L21/762 ,  H01L29/06

    CPC classification number: H01L27/1203 ,  H01L21/76254 ,  H01L29/0649

    Abstract: A manufacturing process for a semiconductor-on-insulator structure having reduced electrical losses and which includes a support substrate made of silicon, an oxide layer and a thin layer of semiconductor material, and a polycrystalline silicon layer interleaved between the support substrate and the oxide layer. The process includes a treatment capable of conferring high resistivity to the support substrate prior to formation of the polycrystalline silicon layer, and then conducting at least one long thermal stabilization on the structure at a temperature not exceeding 950° C. for at least 10 minutes.

    Abstract translation: 一种具有降低的电损耗的绝缘体上半导体结构的制造方法，其包括由硅，氧化物层和半导体材料薄层制成的支撑衬底，以及在支撑衬底和氧化物层之间交错的多晶硅层 。 该方法包括能够在形成多晶硅层之前赋予支撑衬底高电阻率的处理，然后在不超过950℃的温度下在结构上进行至少一个长的热稳定化至少10分钟。

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