公开(公告)号：US20210035894A1

公开(公告)日：2021-02-04

申请号：US16940815

申请日：2020-07-28

Applicant: STMicroelectronics S.r.l.

Inventor： Fulvio Vittorio FONTANA

IPC: H01L23/495 ,  H01L23/00

Abstract: A lead frame for an integrated electronic device includes a die pad made of a first metallic material. A top coating layer formed by a second metallic material is arranged on a top surface of the die pad. The second metallic material has an oxidation rate lower than the first metallic material. The top coating layer leaves exposed a number of corner portions of the top surface of the die pad. A subsequent heating operation, for example occurring in connection with wirebonding, causes an oxidized layer to form on the corner portions of the top surface of the die pad at a position in contact with the top coating layer.

公开(公告)号：US20200176363A1

公开(公告)日：2020-06-04

申请号：US16782797

申请日：2020-02-05

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Cristina SOMMA ,  Fulvio Vittorio FONTANA

IPC: H01L23/495

Abstract: One or more embodiments are directed to quad flat no-lead (QFN) semiconductor packages, devices, and methods in which one or more electrical components are positioned between a die pad of a QFN leadframe and a semiconductor die. In one embodiment, a device includes a die pad, a lead that is spaced apart from the die pad, and at least one electrical component that has a first contact on the die pad and a second contact on the lead. A semiconductor die is positioned on the at least one electrical component and is spaced apart from the die pad by the at least one electrical component. The device further includes at least one conductive wire, or wire bond, that electrically couples the at least one lead to the semiconductor die.