公开(公告)号：US20230161485A1

公开(公告)日：2023-05-25

申请号：US17993618

申请日：2022-11-23

申请人： STMicroelectronics (GrandOuest) SAS ,  STMicroelectronics (Alps) SAS

发明人： Loic Pallardy ,  Nicolas Anquet

IPC分类号： G06F3/06

CPC分类号： G06F3/0622 ,  G06F3/0637 ,  G06F3/0673

摘要： In accordance with an embodiment, a system on chip includes: a plurality of master equipment; a plurality of slave resources, where a slave resource of the plurality of slave resources comprises a memory device includes a first memory area; an interconnection circuit; and a check circuit. A first master equipment is configured to define initial access rights for the first memory area, and to delegate access management of the first memory area to a second master equipment. The second master equipment is configured to define for the first memory area, particular access rights from the initial access rights associated with the first memory area and access right rules; and the check circuit is configured to check whether a transaction intended for the first memory area is indeed authorized to access the first memory area using applicable access rights associated with the first memory area.